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6.1.5, DRC err on tStop layer...sometimes

e14 Contributor

Hi,

 

Most likely my error someplace, brand new to Eagle CAD. Anyway, my

question is: Is tStop layer invisible by default? Reason for this

question: I was down to zero DRC errors on my first small board layout

with Eagle, then I notice part of the perimeter (layer 20) had vanished

on my layout. So, I turned off view of all layers, then turned on just

layer 20 so I could redraw the border outline. Fine, done with that,

turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

How is it possible to not see this before? Just for fun, I turned off

tStop layer and ran DRC again. No errors! What the heck... can anyone

shed some light on this, is there something I need to fix? By the way, I

did 99% of this layout with original default design rules, then found

that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

see errors before turning on ALL layers. Should I be concerned about

these errors I almost did not notice before ordering boards? I made

Gerber files & looked at them with GerbV, they look fine to my

eyeball...but i don't perceive 3mil objects all that well! That seems to

be the top solder mask min/max in the SunStone rules.

 

Thanks for any enlightenment,

Bill

 

Parents

  • Bill Martin wrote:

    .................. I have not found any way to make these tStop errors

    go away, short of just turning off visibility to layer 29. This does

    not seem normal...or correct. Maybe the thing to do is just submit

    the files to SunStone & see if "their" DRC passes or fails.

     

    Best Regards,

    Bill

     

    One of the most usefull and common actions a  board house will do is post

    process your design to remove any silk sreen that is not on top of solder

    solder mask.

    As always you need to confirm your chosen board house does this.

     

    Generally it is accepted that you should have your libraries as correct as

    possible in this matter. Names that are smashed and moved later should be

    placed sensibly to prevent placement in mask clear areas. The board house

    then chops out the remainder

     

    HTH

    Warren

     

    --

    Viewed / responded via the newsgroup at

    news.cadsoft.de

     

     

     

Reply

  • Bill Martin wrote:

    .................. I have not found any way to make these tStop errors

    go away, short of just turning off visibility to layer 29. This does

    not seem normal...or correct. Maybe the thing to do is just submit

    the files to SunStone & see if "their" DRC passes or fails.

     

    Best Regards,

    Bill

     

    One of the most usefull and common actions a  board house will do is post

    process your design to remove any silk sreen that is not on top of solder

    solder mask.

    As always you need to confirm your chosen board house does this.

     

    Generally it is accepted that you should have your libraries as correct as

    possible in this matter. Names that are smashed and moved later should be

    placed sensibly to prevent placement in mask clear areas. The board house

    then chops out the remainder

     

    HTH

    Warren

     

    --

    Viewed / responded via the newsgroup at

    news.cadsoft.de

     

     

     

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