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DRC Settings for Advanced Circuits

autodeskguest

Hello everyone,

 

I have a customer who would like to use Advanced Circuits to manufacture

their board(s).  However, AC requires 10mil clearance from a drill to any

other feature on an internal layer.  From what I understand, this is the

edge of the drill, not the center.

 

I can't figure out a way to account for this parameter with the DRC.  Can

anyone come up with a creative solution other than writing a ULP to detect

this?  I know I ran into it before and just went elsewhere (yes Terri, to

Sunstone).

 

Cheers,

 

James.

--

James Morrison  ~~~  Stratford Digital

 

email:  james@eaglecentral.ca

web: http://www.eaglecentral.ca

 

Specialising in CadSoft EAGLE

  • Online Sales to North America

  • Electronic Design Services

  • EAGLE Enterprise Toolkit

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Browser access to CadSoft Support Forums at http://www.eaglecentral.ca

 

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  • "James Morrison" <james@eaglecentral.ca> wrote in message

    news:him1m8$7nj$1@cheetah.cadsoft.de...

    I have a customer who would like to use Advanced Circuits to manufacture

    their board(s).  However, AC requires 10mil clearance from a drill to any

    other feature on an internal layer.  From what I understand, this is the

    edge of the drill, not the center.

    I can't figure out a way to account for this parameter with the DRC.  Can

    anyone come up with a creative solution other than writing a ULP to detect

    this?  I know I ran into it before and just went elsewhere (yes Terri, to

    Sunstone).

     

    The different signals is easy I guess? The same-net is worse. They can get

    down to infinite small, no matter what you set your DRC rules to (like where

    you have a via close to a wire of same net). I hope Cadsoft will do

    something to that, so we can see it in the check list.

    I have a drc to fill via-via (inc pads&smd) and polygonfill-via, but not

    wire-via. Would that help? It may need some tuning as it is only tested with

    my 16 layer HDI type II stackup.

     

     

     

Reply

  • "James Morrison" <james@eaglecentral.ca> wrote in message

    news:him1m8$7nj$1@cheetah.cadsoft.de...

    I have a customer who would like to use Advanced Circuits to manufacture

    their board(s).  However, AC requires 10mil clearance from a drill to any

    other feature on an internal layer.  From what I understand, this is the

    edge of the drill, not the center.

    I can't figure out a way to account for this parameter with the DRC.  Can

    anyone come up with a creative solution other than writing a ULP to detect

    this?  I know I ran into it before and just went elsewhere (yes Terri, to

    Sunstone).

     

    The different signals is easy I guess? The same-net is worse. They can get

    down to infinite small, no matter what you set your DRC rules to (like where

    you have a via close to a wire of same net). I hope Cadsoft will do

    something to that, so we can see it in the check list.

    I have a drc to fill via-via (inc pads&smd) and polygonfill-via, but not

    wire-via. Would that help? It may need some tuning as it is only tested with

    my 16 layer HDI type II stackup.

     

     

     

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