List of common bummers

Morten Leikvoll wrote:

Just made a major bummer on a prototype, and I thought first, why do I (and

others) do these errors over and over again.. So maybe its time to collect a

list of common bummers. There should be a checklist for common errors, maybe

even included in the DRC box as plain text! (Hey, Ill post that on suggest!)

 

Here is my recent ones:

 

1. PCB board thickness when using edge connector. In the heat of picking a

stackup for a 10 layer board, the stackup suggestion from the manufacturer

chose their own thickness (tiny number in a tiny box). Neither we, or any of

the other 3 partners involved in the PCB production ever thought that since

there is an edge connector, the thickness is critical.

2. Part verification. There should be a flag on all components called

"verified", that is set to NO on never manufactured parts. Maybe even a text

field for a "verified" attribute. I know very well that is a common problem.

Either pitch is wrong, pads are wrong size, pin numbering is

mirrored/interleaved or wrong somehow. Recently, I managed to mess up the

pinout of a CF socket. Pin numbering should be interleaved, but I managed to

do them sequential. I also managed to mirror the 4 wire pairs on a ethernet

connector.

 

Please submit your own bummers (and don't be ashamed, we all do them)

 

 

 

Good ideas Morten.  I like the idea of Verfied check box.  One thing I

do now if have a verified and unverified library.  I make a part in

unverified and then copy it to verified once it is produced.  However

this process is troublesome and time consuming.  Some other way to mark

a part would be nice.  One method is in the part description.

Another check that could be added to the list:  Silkscreen overlapping

with holes or vias.  Some design are complex and I will miss an overlap

which will ruin the silkscreen.  Maybe there is a way to check for

collisions already, but I haven't look into it.  If there isn't a way,

perhaps a way can be created.

In the CAM system one can build there own jobs and the who, what, where,

when, and how of a design output.  I like this.  Perhaps some sort of

similar system can be built in DRC so that one can set workflows and

levels through the work flows.  For instance, when I am routing a board

I want to know clearances, but I don't care about text or overlaps just

yet.  It would be nice to run a "partial" DRC on just the portion that I

care about.  As the design nears completion I care about the finer details.

Morten Leikvoll wrote:

Just made a major bummer on a prototype, and I thought first, why do I (and

others) do these errors over and over again.. So maybe its time to collect a

list of common bummers. There should be a checklist for common errors, maybe

even included in the DRC box as plain text! (Hey, Ill post that on suggest!)

 

Here is my recent ones:

 

1. PCB board thickness when using edge connector. In the heat of picking a

stackup for a 10 layer board, the stackup suggestion from the manufacturer

chose their own thickness (tiny number in a tiny box). Neither we, or any of

the other 3 partners involved in the PCB production ever thought that since

there is an edge connector, the thickness is critical.

2. Part verification. There should be a flag on all components called

"verified", that is set to NO on never manufactured parts. Maybe even a text

field for a "verified" attribute. I know very well that is a common problem.

Either pitch is wrong, pads are wrong size, pin numbering is

mirrored/interleaved or wrong somehow. Recently, I managed to mess up the

pinout of a CF socket. Pin numbering should be interleaved, but I managed to

do them sequential. I also managed to mirror the 4 wire pairs on a ethernet

connector.

 

Please submit your own bummers (and don't be ashamed, we all do them)

 

 

 

Good ideas Morten.  I like the idea of Verfied check box.  One thing I

do now if have a verified and unverified library.  I make a part in

unverified and then copy it to verified once it is produced.  However

this process is troublesome and time consuming.  Some other way to mark

a part would be nice.  One method is in the part description.

Another check that could be added to the list:  Silkscreen overlapping

with holes or vias.  Some design are complex and I will miss an overlap

which will ruin the silkscreen.  Maybe there is a way to check for

collisions already, but I haven't look into it.  If there isn't a way,

perhaps a way can be created.

In the CAM system one can build there own jobs and the who, what, where,

when, and how of a design output.  I like this.  Perhaps some sort of

similar system can be built in DRC so that one can set workflows and

levels through the work flows.  For instance, when I am routing a board

I want to know clearances, but I don't care about text or overlaps just

yet.  It would be nice to run a "partial" DRC on just the portion that I

care about.  As the design nears completion I care about the finer details.