Good practice on 4layer pcb for noise immunity

Pedro,

It's very convenient to have a ground and power plane, but in many cases

one should consider using a star power and star ground architecture.

This minimizes noise from one IC from interfering with the operation of

another.  Ideally each component would have a ground line from its

ground pin directly to the power supply ground.  Same goes for power.

This can't always be done, but emphasis should be to keep all analog

devices on their own analog ground, and digital devices on their own

digital ground.  Both grounds can be tied together with a SHORT device

in close proximity to the power supply ground.  The power planes do

provide some capacitance, but it's such a small value that a .1 or .01

uF bypass cap will swamp this out.

Another suggestion is to keep the traces on one layer orthogonal to

adjacent layers.  This minimizes the capacitive coupling from one trace

to another.  So one layer should be designated for traces that run

horizontal and diagonal from top left to bottom right, and the adjacent

later should be designated for traces that run vertical and diagonal

from bottom left to top right.  The idea is to minimize the stray

capacitance between signals.

Of course, for every rule there are exceptions, and it's up to the

designer to identify which rules to follow and when to make exceptions.

HTH,

    - Chuck

On 08/12/2014 02:07 PM, Pedro Pinto wrote:

Hello,

I want to design a 4layer board and not know what is the best practice

to make best immunity to noise

I plan to put the components on the top layer and layer2 all as GND, the

layer15 as VCC an the bottom layer for the rest of route. The top and

bottom layer i want design a poligon that connects to GND

 

Anyone have experience with this and can give a ideas if what i want do

it's correct or not?

 

Thanks in advance

Best regards

Pedro

 

--

To view any images and attachments in this post, visit:

http://www.element14.com/community/message/123592

Ground filling the top and bottom layers may or may not improve matters - the problem is that you may end up with a large number of small islands of copper connected to ground by thin tracks. If this does happen you need to stitch these islands to the ground plane with a large number of small vias.

However it may not be worth while -  for sensitive analogue circuits putting ground plane under some parts may actually make things worse.

If you have a relatively small number of connections to VCC it may be better to make these by track and use the "VCC" layer as a second ground plane.

If I were you I would get out of the habit of calling any power net VCC, call it V5 or V33 or some name that tells you what it actually does - I've seen some horrible disasters when chips with VDD and VSS ( and other oddly named power pins) pins get mis-connected to  VCC  and GND.

If you want to post  a .pdf (not Eagle format - I can't read it) of your top layer I might be able to offer some more ideas.

MK