Testpoints for ICT testers

Michael Sansom schrieb:

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

Not to my knowledege.

Ideally I'd like to know the percent of nets covered by testpoints and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

You could write an ULP that collects all net names and then checks which

nets are connected to testpoints (which should be identifiable by a

common prefix, for example). The easiest way to provide the results is a

list containing covered and uncovered net names - and that would also be

sufficient for your decision.

I don't know if such an ULP already exists.

Tilmann

Michael Sansom schrieb:

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

Not to my knowledege.

Ideally I'd like to know the percent of nets covered by testpoints and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

You could write an ULP that collects all net names and then checks which

nets are connected to testpoints (which should be identifiable by a

common prefix, for example). The easiest way to provide the results is a

list containing covered and uncovered net names - and that would also be

sufficient for your decision.

I don't know if such an ULP already exists.

Tilmann

On 12/28/2010 2:12 AM, Tilmann Reh wrote:

Michael Sansom schrieb:

 

>> Is there a way to systematically insert ICT testpoints onto a PCB layout

>> without putting a testpoint component on each net on my schematic?

 

Not to my knowledege.

This is quite unfortunate.  In any engineering company I've ever

participated in of even a moderate size, the insertion of test points is

normally a post processing function, done by the PCB designer who more

often than not is not the engineer who generated the schematic.  The PCB

designer is generally tasked with inserting test points so as to insure

that a minimum fault coverage is achieved during ICT (say 90% perhaps).

  It is generally solely a function of the manufacturing/quality control

people to determine what test coverage level they desire and to insert

the test points to meet that level.  The design engineer generally

neither cares nor wants to be bothered with that information.  Only if

there are particular nets of interest that the design engineer wants to

ensure to be tested at ICT will he explicitly insert test points on the

schematic, and typically this will be for a very small percentage of the

total nets on the board.

Practically, having to insert all testpoints on the schematic results

in a cluttered, less readable schematic since you will in general want

to cover a high percentage of nets (ideally 100%).  If this is not a

planned feature for future versions of Eagle I would encourage CadSoft

to seriously consider it.

I would think you would accomplish this by having a special class of PCB

components which are specifically excluded from consideration when

doing a cross check between the PCB layout and the schematic netlist.

-Michael