Is there a way to systematically insert ICT testpoints onto a PCB layout
without putting a testpoint component on each net on my schematic?
Ideally I'd like to know the percent of nets covered by testpoints and
have someway to highlight or locate nets without a testpoint so I can
either add one or can decide that the particular net isn't worth the
trouble to test.
-Michael
Michael Sansom schrieb:
Is there a way to systematically insert ICT testpoints onto a PCB layout
without putting a testpoint component on each net on my schematic?
Not to my knowledege.
Ideally I'd like to know the percent of nets covered by testpoints and
have someway to highlight or locate nets without a testpoint so I can
either add one or can decide that the particular net isn't worth the
trouble to test.
You could write an ULP that collects all net names and then checks which
nets are connected to testpoints (which should be identifiable by a
common prefix, for example). The easiest way to provide the results is a
list containing covered and uncovered net names - and that would also be
sufficient for your decision.
I don't know if such an ULP already exists.
Tilmann
On 12/28/2010 2:12 AM, Tilmann Reh wrote:
Michael Sansom schrieb:
>> Is there a way to systematically insert ICT testpoints onto a PCB layout
>> without putting a testpoint component on each net on my schematic?
Not to my knowledege.
This is quite unfortunate. In any engineering company I've ever
participated in of even a moderate size, the insertion of test points is
normally a post processing function, done by the PCB designer who more
often than not is not the engineer who generated the schematic. The PCB
designer is generally tasked with inserting test points so as to insure
that a minimum fault coverage is achieved during ICT (say 90% perhaps).
It is generally solely a function of the manufacturing/quality control
people to determine what test coverage level they desire and to insert
the test points to meet that level. The design engineer generally
neither cares nor wants to be bothered with that information. Only if
there are particular nets of interest that the design engineer wants to
ensure to be tested at ICT will he explicitly insert test points on the
schematic, and typically this will be for a very small percentage of the
total nets on the board.
Practically, having to insert all testpoints on the schematic results
in a cluttered, less readable schematic since you will in general want
to cover a high percentage of nets (ideally 100%). If this is not a
planned feature for future versions of Eagle I would encourage CadSoft
to seriously consider it.
I would think you would accomplish this by having a special class of PCB
components which are specifically excluded from consideration when
doing a cross check between the PCB layout and the schematic netlist.
-Michael
On 12/28/2010 10:25 AM, Michael Sansom wrote:
On 12/28/2010 2:12 AM, Tilmann Reh wrote:
>> Michael Sansom schrieb:
>>
>>> Is there a way to systematically insert ICT testpoints onto a PCB layout
>>> without putting a testpoint component on each net on my schematic?
>>
>> Not to my knowledege.
After a few more minutes of consideration, I don't see why Eagle
couldn't treat testpoints exactly the way they currently treat plated
holes. For instance, on the board I am currently working on, I have
four plated thru mounting hole. These holes are electrically tied to a
net (GND), and yet they appear nowhere on my schematic. They were added
during the PCB layout process and have nothing to do with the schematic.
Like testpoints, they are single port elements, i.e. they make one and
only one connection to a single net, so they do not interfere with the
functionality established by the schematic.
Clearly, Eagle already has a mechanism for handling single port elements
that are added to the PCB manually but not to the schematic. A
testpoint would simply be a similar element that consisted of a single
non-drilled pad.
"Michael Sansom" <mssansom@hotmail.com> wrote in message
news:ifb4bo$pg7$1@cheetah.cadsoft.de...
Is there a way to systematically insert ICT testpoints onto a PCB layout
without putting a testpoint component on each net on my schematic?
Ideally I'd like to know the percent of nets covered by testpoints and
have someway to highlight or locate nets without a testpoint so I can
either add one or can decide that the particular net isn't worth the
trouble to test.
-Michael
Hi Michael
Your requirements to reconcile net names with test pads and have a freely
placeable copper object in the layout editor would likely require a new
special object.
I imagine an object that is similar to the via, but un-drilled and only on
the top or bottom layer, would work to some degree.
What you are left with then is, like a via, only being able to determine if
one of these objects has a net name the same as a wire (routing). More code
is required to determine if they touch.
For now the following idea may be acceptable to you. Doing it this way you
will be able to get all the net name reporting you require, after a ULP is
written.
It does involve the schematic but visually there is only an increase in the
number of 'junction' dots displayed. I would expect that in most instances
you will use the junctions that are already drawn and occasionally have to
place one on a net wire.
The test points symbol is mostly on a new User layer which you only display
when needed.
The attached image shows what I mean.
Packages for these test points need placing in the layout editor but there
will be an airwire to assist.
Using Devices with multiple packages you can conveniently "Change Package"
in the board editor to lay down a differently sized test point that is more
appropriate for the available space.
If the test point needs to be away from a trace, this method lets you route
back to the trace as there is a valid net connected (airwire)
The 'Show' command displaying the complete net assists with choosing the
optimum place for the test point.
A ULP could now identify which nets do not attach to an element (your
various test point styles) with a nominated prefix.
One of the current assembly ULPs could provide the XY locations of the test
points and maybe their related net.
HTH
Warren
begin 666 ICTPoint.gif
M1TE&.#=AO0(S`?<`````````0 ``@ ``_P`@```@0 `@@ `@_P! ``! 0 !
M@ ! P!@``!@0 !@@ !@P" ``" 0 " @ " P"@``"@0 "@@ "@P# ``#
M0 # @ # P#``#_0 #_@ #__R ``" `0" `@" `_R @`" @0" @@" @_R!
M`"! 0"! @"! R!@`"!@0"!@@"!@R" `"" 0"" @"" _R"@`""@0""@@""@
M_R# `"# 0"# @"# R#`"#_0"#_@"#__T ``$ `0$ `@$ `_T @`$ @0$ @
M@$ @_T! `$! 0$! @$! T!@`$!@0$!@@$!@T" `$" 0$" @$" _T"@`$"@
M0$"@@$"@_T# `$# 0$# @$# T#`$#_0$#_@$#__V ``& `0& `@& `_V @
M`& @0& @@& @_V! `&! 0&! @&! V!@`&!@0&!@@&!@V" `&" 0&" @&"
M_V"@`&"@0&"@@&"@_V# `&# 0&# @&# V#`&#_0&#_@&#__X ``( `0( `
M@( `_X @`( @0( @@( @_X! `(! 0(! @(! X!@`(!@0(!@@(!@X" `("
M0(" @(" X"@`("@0("@@("@X# `(# 0(# @(# X#`(#_0(#_@(#__Z `
M`* `0* `@* `_Z @`* @0* @@* @_Z! `! 0! @! _Z!@`!@0!@@!@
M_Z" `" 0" @" Z"@`"@0"@@*"@Z# `# 0# @# Z#`#_0#_
M@*#__\ ``, `0, `@, `_\ @`, @0, @@, @_\! `,! 0,! @,! _\!@`,!@
M0,!@@,!@_\" `," 0," @," \"@`,"@0,"@@,"@\# `,# 0,# @,# \#
M`,#_0,#_@,#___\``/\`0/\`@/\`__\@`/\@0/\@@/\@__] `/] 0/] @/]
M__]@`/]@0/]@@/]@__^ `/^ 0/^ @/^ __^@`/^@0/^@@/^@___ `/_ 0/_
M@/_ ____`/__0/__@/___R'Y! ``````+ ````"]`C,!``C_`/\)'$BPH,&#
M"!,J7,BPH<.'$"-G$BQHL6+&#-JW,BQH\>/($.'$FRI,F3*%.J7,FRI<N7
M,&/G$FSILV;.'/JW,FSI\^?0(.>E'20$%)2)$636I4J-.G4-G4JUJLFF
M1[-J'8CU7U>K8,.'4NVK-F27;%^]<JUZ-FW<./G4O7:=JV"M?6W<NWK]^_
M@"G>%:@7;^##B$6N3<MT:=$D",_;*IV86')F#,G7R5AUD'/?].?FIAIHL;1P8`H/S>\K=RY^/D+U]
MS#98]1/\WY[FUM!QV !-'WT4'DI1@00NZA)] #]'''(4NE;_X(7)-3B1
MAB!Q('*BT(HG?:45C=B1BF>)N&]S'8(H3^?=A>A .]"..--OKW'T$>ZECC
MCCR2-^--YH$']$%JG<>>I]UJ24,6()(:=!5%[Y8T(C?AFD
MF&-R&:.+!W5)9I1^A3E6A$JRN9.(6&X)I)!XBJFED7L:F>:=8'HYYJ!E`IHG
MFH2Z:=&.BHJDJ.!UG3FH82Z!\BE5-'IHXPV)EJGGX6":F:D]6T:HR;@LBB
MG90N6ADI+YJ*@OP=DGK>1=JNM4= ::XZ=Z`DOEH3W.>NNPN":[9K"MNCH2
MK6>5.Q,O:X)[6VZ8BI5M0N-:BVKS'JZ_VRSHM9YZ*Q^GFNL
:VBFG9K:8
M)"=#OOKNY42NE]<XXI;MVXC?I=]GN&M6_>A(KB#(JONK/D;.Z=WHYH
MJZ#LNL1P@UC^2VX? IJZ[@D_UENN/!RC.ZZ!!<,R+8`#_FNO .CNS"\![9
MZ(])HJNOM]W.C'-T!M_$[:DZ\PORJ<="K&C%&"-M<M(G6^JRMI!=FQ_$&C]4
M,$Z:GFDJPR'GZ7#'Z;HXJ<.-+DWURD-[M^O7ZW$-MMU=-T2W34>K/?*W59\-
M]-L0UVRJ@`#7EZV_[A<MU!:YRW0U493C#?:BO<I>-0*_TSN1&W>F[DIQF,
M:=&2IUX2Y7S3*V&RPK"CO'G)H<?[>>P6VZYXR]J>CKKJP'MT-=;4QJQED33C
MVV_5-NML*LV=V\QYJ4JR?!W6O;\<_/;"^_Z[6:2W%#[W`Q%/_OD8,>XX7..'
M>#GZ"YD/__P1F?[R]V2UGY^G>33___\;-?X_ 'P ZKX ( CVM'? !-*O
M@0Z,X.2T)\$(0K""";P@!LGP0WKX,>3)VNV /"$/:/@B:D'_]2Z*H2LK!K
M`(# "RV(PAF2+X8VS& -<Q@\",B0A_,;(0!<"$0H^;"(_ULA$LMSQ"7"#X=.
M5%T3HWC#'U(Q;U.\8@^MJ$5V9;&J?LB&.4DQC%JK(QF5!$:T[BH-;#L4!N
M?*,1N2C'%,6QCABZ(QZ92,<]1DF/?O0.( ,IGT$2,CJ&/.1W$JG(X3"RD=)Y
M)"1M(\E)$J>2ED0-)C-YFTUR4C.>_&1J0BGR)"RE$Y)2H_8B'"/(DKK_R(
ME<IF5G2<B.MW(Z .F++6RFE[[$"' LU$J/`#.8?SDF,@53(<NL1)G+W LT
MHPF1W#A3)=.D)C,'Y,K'T":6QNRC-ED"GVNF))OCC$@N322>=H8SG3 I9UZ>
M4YXNF28SBDF+MI_\KJ"8^V.1G/U5BS7D&= I(<TN2V,2=/Y$G\()7D&M
M<U"$#B5 W&R-<V0IT/=LU"L1E>@_S8D2AUJT,A_5Y4A,VI-UAA1X\J3H.3MJ
M48Z@U#%*:8W1<)2GA 31?+Z7@J6M.0H&>G/.GI3B!:0(6R,Z,-I2E=F$J^
ME\Y$J3JA:E Q^E3NZ),C6,U),7//:O)*PXT2K];LI.E?)4JG-QZ?G,&A.T
MWD2M\V.KDY *2[YR%#(_=2<M[6H3O%;UJ'1E"6%K8MC!PE4NC9VK4Q9+D\BB
MDK5[6IBG;59EV!6)I8MY6=G@IZA;E4HHXWG1P6[RM0652>NO>=J.^O'V"^
M]B:V)>=L0RB(LS[VMLG\[7(TZ\'>]A8FN07N586[''"R_[: Q_U'=%N27.76
ME;G6Y4AO(8##Z084N]F52W6UN5WN^A "WCW)><<;7GJV-R7E->\1TTN2]9[W
MO9!A+S*/>]X8WI>;[5O689'X (;, (3K""%\Q@`]-'OUVTKX0G3.'^]K=1
M/O1OA3?,X0[?=RP-#K&(1TSB$BN8.9%H2UZ.$66WB]&LZPBV=,8[*8^,8X
MSK&.AS<6&8=5P/@M27PU+-WOKM?&1,16DI/J8_!B9,)!%K(@?"P(`-?WR$C>
MH=R6O),7Q76=ZQF,=,9@=/I;Q65J3%:/3G'Y-00L"8UGW+8YV]G#82ZS
MGO=,9JI,^7TK73-(R%J=E\99.J"'#O2=6QSC13L:S&+ALZ0GG>.J0/$EHYT0
M4+WVYM0D>K)-5JR$LSR?3_MDL:[5*T1,31Q6!\7'GL4RB#N-&E=W6= :2756
M_!I +6/'UJ_&=49TO5<W^_IZM%[N=>]ZE/ P!-A*/O944"WLCA#:JZM.MFB@
MC1-J,WNDG)8VT;3=[6I?)-/BV2RW8;-NFWB[L)TQ-DUTVXFQO>W=';O#-3
M_V:O)NQ\<ZVN%E#F28=M:](_6I0@U;<UN$V)[AM4(8ONU]Q_K>`&_VM9\-
MPL%X'#FY8<Q4%YNC&<6EOD^",GI;7'J.KPBS:V0SZN%9K77.126;F[7TX1
MB=;X5NN:A-'NF.@]RTJ_F*432M::CHO";_/OF)Y#WPY#S=Y40/"ZM#SAB#
M0X?IS_W)U96MXF]/'>@-X3I9#][-A]6&,_R*/G3O>ZV]W#)"SSS)_J39OC
M9>G/H6U,XIYU]^(;X3)/^]%KOOC6X#PJA"_(W2=/^<K?.>]]5CQ#D][XOT=\
MTPL7NF\+;Y6M=S[PIP_\XYTN>J)>?,!&9[SL/;_X"?\)'B:1QS3/)Q)SM#/$
M[Z4!_-&=FO/6SY3T57$U=8 O?(T6>N3&USWRJ6+ZK?"5[>X$//$A'WTU3[\E
M7=_XQ%UX?8.7MNV$7C[TJPX2R[O__?"'\1#UKOG9]#WUPK?]^JL2== NE./L
M-QRYIQ#Q5X &:'>8-V9[MWFH-WNTIW_%%X"W]GT$]7,4,8" @8%#5W:PQW[,
MAR-]X -R'T2V' 4N!)JX5P)H8%P8*NAW4=.!G.1WLT'PV2(\MWL2X7.J
M-GXE&&UET7@M5?BMXD=VWG!UF]R3J%X$Y>((5B'0`&'0_!-"&$__UVM4
M(0<F'%O9X15R&[=!X/2EUD>/>@0+L@7:1@25ZA:X(:&8_@7:A]72AU2EB$
M8+B%_U31AB]Q4U95?8ZW4]B'?7>(AW 7AX97AEYH@7 8AG"&B($&A0E%A(GW
M>Z+Y'4JSXBR!(<,D7AHXD 198>RX8[(6OZ8?9OH
MA"B&CPWQC(V8D L9CPNY?WL(D0PAD:)(D?_83IC(BJ6'C>>QF(M@D8HB^9%*
M]Y$8.6T:N1 <V8WUYVP5V4RS9HXYP8?4MXO?&'[4>(D!B9.RV'XON1*V5G[A
M"([I1VJB5I!.69 'J6,>66P@Z8OH1XZX1Y*XJ(U%)Y0LYY4[^)1BJ8Y166G>
MJ) J68TWR85<J8M@B1G+:(HF.9(>")15R9!AAX,9.92OJ)7Z)>1.)=!8.:
MV(\LB94T$9>Y5I0)$9.U:#5OZ6^,B1".Z8/5A(1*67!,R)0NR9=B!YAPH9A$
MZ9D(9IF89KG-IERIYHG@9J<18ZV9`YJ29H]X9IK9"VR1.XV97_;/EZ
MKYDKM#F:@KF3D1D9OBB@$(H3'<J?4O&A
M*(%29VB@&QH8-:J<,WH3/ZJA'I\:75VT/B>/7J=3JB2EJDPRA62#J13XJA
M"GI/(6J(;JD<JBB81FD-O6&'5FE,IJA_O2B+ON8GPDZG: HIC9G?IYI;J%
MIDE*HE&!HY,8<'5J4!7B5_-X%D-:C"9J6R$(HV3_>J.#:J(,M:-;>I:MR(AY
M&8-6RJ8GQZ@&$:C7R57IGL?%A.#(\.I4KB9=T@:GW":XY*:/":=K:F2=
MZJ26N(K'6*I>F2):G:0J9JVIDN!V0(.I/YAIA$.JE-ZH:J:IFQVJ<;]Z?0
MJ:F!V91CF6'SEWG NHG"A2FZJ&W:H=3.J;\AL=:VW6:O.V)S1G]Z5DVY
M.JMSD:T1N9Z^BH7@6(G\&)VNA?NRIRQ%J\JJZJ=J]UD:\P::ZC9J%2&)*N
M)?.*I?0JK]JJXF$JYJ2*[JN:^R!JO)RHT)&Q<"RYX#ZK 8ZZAWJ%/B.JX+
M&Z6]>JYEB6.$B6VT.+$GOTN<<NJB5YFF%UJF#3N6*WMC_GJ,)1MZ,?M79CH4
MYV&S6Q:T<D:P_%J?,OBO5AFP%*NMJ'H13<>NEQJU-AH6: 5I(9NL8FJIDLJK
M,PM^XNL=@H6A 6R#]NR&J=TH JH6N1V[J(&ZM <3NL.$NIGMJV6FJW2*NP
M4)J-W-J0H7JH6CNWI%6T>[JKB#JU1581"F>VK)JWQ2I;)6*TOW:W!(BX&V%<
MD M5WOI[]_=U2+F4-R>.I:FYY>JX5%NV(SJY_XT[M X176G&IW7KM^Y8M9\W
M@X69A>:INJ<JNV=JC9++N'?*N1=19516N[LE$:E8D[SXJ'>9J7&JM\9JM5?[
MMQPOLYHT/V7RS!;1<IJX:)O33O>_NA81N:]KO%"!IPS!7Z'VN"EQE8
MDC]IE[=K$QW;F,B[M\1;O'DQNB!7NGJU=(28NEQZK@S,8?Y59TTF83MK8A/1
MA&JIOX0[G@KMK[N0'<OJ&HNVSAAS8)D-@JD V<PA/6:"R\81-<8A6\:Q3E
M&FY%O<1ZGXOI7_FXO^7#D] KO=+KNQJLO1L!O_%[HJ'&O"#QO#(,;C3<5GA;
MHF#J92XAOBQ)ON,;J?\1NL$$8<3Q^V+TJQ),W(N\RXBC:L.4B\.V*E_-:;\D
MK'''D<4_.Q]B\1@NEW=5<4E%$MNBYE^*GYS!WJ,$+,$8UF$O3&(Q7)C1
M6[X\G)A<[&H2KO61J_NZ[7J6<B:#&-T-JT**!&5H;A/3,9H'MC2Q&>:U-_
M&,F\241]NYVGALK,=U.5(2UAR',7'Z[A*W.8BVP2,X];^9K,.TG+M0
M7,9O;Y"RLIVPHF,&X:[@B.\Q3FV(OH7Q^2K3V&:@J\"!6Y)+)<T$4<=#
M#,JG1LQ'LN(EF2!#30G=:7,[.?,[JE,X=K,J6?+,S]\Y?&LS2,X]3,0S
M;P%M_FRK:P1P@S"1O+4?._H>ZJQJ@=C'XT8C1I[U;B\I7NSODOQUHU(9DKTSU/-U'#]=H6JIR[[
MR*T;TQ
S1#TRHVV.G:M#X[PU\X.5I-@US=:Y -:#(;V@:NK8KD@`[U!.7
MVA:XV@)LUV9-BL&\KK6-U;?=UDZLUME;O94[F&=IU<]EVRN(V^LCJ-L,#6KT
M`6Q<?<N93;A%';%7W-6MJL9KF['!:MK&O=UN;7^53=TQFI!MQ\W_Q*SF;94<
M_==606VB37_5VMSDW54\%M+G_;2BV-HH2\T-/1ET#=MJ=M_4JG@[*LJGW3C0
MW7S2S:,"KBP>\D4/8'K;8E.BY?.C8RXK:/&[=FF?8%#MAE3>"S#:DN_<'Q
MC:0R/=)>;77U/-8&_K:P;.(K/K*4^-XX_N)]?> R_MW\C.$;==(]IZ@EO>&6
M(>1?S>0G?L\:KN+ _-D?#>69&X9(#L]4WLYH;8)8?A:()=]O=M(M62K>-5
MWL\X_]ZB40Y9%^S(LLVG:)[F%U[DMEOG_EO=-1[5F0BP<S[ K]S;I=/GS:SE
MH-WE97'&$C[B]/S4^\3GD&ZP*.[F6>Y1$=OA@3[CK6;H:<=V0=[FC\ZV>AXM
M86X68]YLCAW@8Q;9@BKIF.Z 64S?IE7JIHY3?>S;L2[4Z/W8K>[:0JOHV1'G
M@.[=.,6_OF;4\]REDXX6F$W;Z4WD;SY<-LF-(57'_C/*30VSL:Z)LV[FTG[I
M=7'=FF[L?>GHS-R"GI[4NOL;93[=F0+LO"'6-_Y*>2W0>^;J1HCNV_Y02/G3
MXOXF$"/1HIZ!ZVY.O [@`%CA)B$_PE'P0='BT>[EL ?49:H,EP>?YYS=V74-
M??S>[SY%OE2JYAX/NI==<<U.$A,EY;F1\/\@\%\_1^Z!7/\9H-M2D_$AO=
M'/,-[C4!00XOY8L><8/>\7<^DA]OZXKQ[RNM'#4*]%JF[3#?4B@GTC./[#F?
M/COT\$4?\=:WOU?_\U@+]18/4C?O$]B]Z6L:RO]*PD\FI/\4/,."FZ&7S<
M]>#!W1//M_#XJ4GIY*6LBR^_[$_!W"U/X_]9[]1T?[68<=U-G\P9%>/=>>[[
M;O-GC_9$C].G#LGC)QE^K_E6CI:D7-#H2_8FW]UA47!@G_$R\?32QOJM[\K6
M"%"A6?JOGQ]>ODA?ZSP+O>'ON!B6((N79%Z/8-K[JLP_C!<??&/VAZ/_)-
M?GZIKM=7V?PAD9R2AEJ=/-I1O1O7![A N_AVV_C<9C=7_93#[1C#?SI[&)
M/&)"3\Z2G[64;Z">GX1.;MVS#_FDG_@`\4_@0((%`15$F%#A0H8-'3X<" $"
M1(H5!P":%%2P8T).P[\*#"D19(E32[$>/#D2I8",Z)4V5F3)HU_Z74R%'A
M2(0\;?Y<B1/H4(;_,8D>A2@1Z4.A%$?Z_/=4YU*J3%]6;9E2ZU:N7;U>Q1H6
M:5.(3R6=10OR[$ZQ;0F2=1M7+DNE<V^"?6@6[5J1>WO:#0L7<-&OA0US'6Q1
MXF+&C1<#`'!8\M><!*%:Y@LR,57!FSTGKJLQK=K1$#M_1DWR=.J[DUUK9=W0
M\6S&D%_?-IIWJD.IL6VN]NW2</"2H9U:UEP2.''FK9LK?W[2>-SE?Y%[W"TR
M.LOJJ'%O9SA==_+#KN#_WP>?6[T#L6W5:_]NO7D]=M7C&\7-^7[&BO
M\A*KS^Y"C0PP8^"PPOWC@2\",!Z5.P(03AZ\J@W+SJC\&RY /1*O8J??3L
M0A(-]' AOTC3,0363,1JPP1<K UV-IL2&H!M1PQ!<!B]&[X5[,D4()30KR
M1Z"2/(H_A6J\Z$;PBF2K2M.@5/) +*/[KD(JYXLJ1(N8S)(F,I>4$B;SS@SK
MRS"M&]-'U7T:$4Q`YRP3.?NVVK!-W$+BH[KYQ33['8__QIR[<*?0O'B4CB
MZ4C\%-6IM_I:#/#-%Q&5<<8H>_3S/D"M"XG'11DUM"I.J4-55,9$LW-0%X\K
M-="-)(VTS%67\G11`IV<\E&3=IRTU53'HK2Y9-&;;:[X;@7S+UPIW'39S8"E
ML=!0@SWI,E.C-/98HG;%D*%(6U0QPF]E:E;<"6%L\I,XXWS1'1K([2-)\;
M]<YH;16SY*HQ?." V]M\%T=^-QW9]H@[BVR/J4[#@02QUMWGG_)3'A1(U=
M-MS/^LU58(!%AC9:"6LMV&'P/%;5QY3]-7>NB".VC>#RCJX8/F.WC>C@/>
MCNCH&H.U-%GE!)!>GS*=5M.A1?]>B>#?1@RZ-ZUM=LS99;<F5;.@3:X09E:S
M;)=5E)VN.6J.RS8:QD)9)F\JEQ]^U>M6GZ;9Z;'OYC)N9>?N"=V=U,4J;;?4
M@[<\C04&?'"J8]N2[I_M[EFL?J_>.U!!"=8Z3UT%9PY+=.&E,ZZ;<9Y8Y\(L
MCA=COA[W.?224^/\#C_)EMS85G*?%9QU1Z=<M]ECKQU6?+V77*\NJ9[]@-
MIM9>W$O4G6:P[=I<QV*'=U<NJVNJ,6N[SY=+<0R-W?XZH"$???)A;;>JYMVU
M'ZS[U"DR&_QLY1<_?#G/N[E7P/"MM\,-8W)?4/60)LV0`!.7.=!_X"K>
M_BX0<2-M45_,^F.]#Z'<PMK5H`%!($IQ>BV>7O=SYFP4ON<&9H^#Z)L@
M#$4GO!G&#(6Y4^'G(+26L:GNA2V)X?5Z."8E4LZ&[:,>8#YH)1XN$5D_Q)ZA
MII@\PF#1BOQKXOR:]$0<7DZ*1T0B$[WXQ2KR:8V^V:+0F.:4087.A/237 :I
M",4BNB6.;X/)&]G8_T6X:1&-W5.M2Q%P@VJ)54R[)0&X>9WK7ID(A4XR"O
M6$BT&3"-JOF:K598LC#A\7:"3$&!S;$E)F279<<%BA1J<G_<?)'ZCM4.GD
MMOLA(RI^25K_EC))P63ECVR)9&Z=D $RLN,*GND,;.HIV$"[EEU.'XD'?"
M"D%&2<NC3?.<URL(KHAVI"2F@B 9,T/6Q)J*9!C+-67:,Y2M[\)C@;(\YQ
M;LM["2PE_ `Y-3W>TI/ 2R3[1,G+BVW3>O8T8B>1QLQ_XK"5U')E<-;)&8BZ
M<+$&X_QZO:FC/IFHS89YL@.NC[8-=21C93C0PMZ(EPV2&IHQTT?=E1#_O"
M4D'=TTL%`[9#.VJSI$[D*6#PJ4Q]2JR?' KI",U8Q'EFZ:0U22EJ-L?(=)[J
MF$.YZE&6RM2F0H"?3]6E1:.H4SV%=29956E)9L8V,"95DVX="EP]NE*;?@B@
M%R5I/;WDTS\15H/'.]E7\54FO>[5L&-\%\,H"=.N&@BO+6DL:![KN8$)U:Z#
MO"S>VAE+S!@NL70$739->U2Y?;8JF74A)EGX/<5RCK&;=908[>.PT%I5FA&E
M)FZS@UA"UI9\O]7L:'-B.=XB]YB]E8YPN47:V=;5N,=U+7!OUNZ$NJZ9GN
M[Y03 U%V78=-\.I=K6\.9PN]3M;":__\3Z)H$MF?D[GJMZ]=R5.R,55G
M>[DVWLI4U[OSS8J 7RM=?O&UKU&M&T/7ZM `9]>/##X:AKM+X5HBF#L*ILI]
MC?C1Q:45.Q(680TMW%,"-VVWM/7P2>I;' T'IZ:=NJDS)VPRUN9NQ>(-+G>)
M&T@`H9<\ZC6A3']:X]B4U:EH]6<Y,S;5ZO78Q^_%,GE+Z]F6QLZ_"AQH@F9,
M$A%?V,EG12M_":@=JG*1H)V\[6+T8^((CW3-E6W/F!7#Y"8O$Z3-O#-@RWLL
M/=.%S\+T<XES?&(["\W*UP+Q4LILYDD7,[)@?ND\'RVD'UM2H@[VH9H3V.;J
M*;FP8:>X9)XWM35IK>.ZN4FG WJ9.V#LHF-B>5-;7IQ!2:(I6^L)99N.H8
M!R72,:U$_4]"]9&^G\WIH.$J7;G,]<$3FF6:)IJE$';VCC<<O\&B
MVL4`MK2VD71L("<;V!V&,.I:.&A"LYLH[VXW?#G\*VG[S]?1-;>.QD=LU'+U
M9T2%M:E11.T5ZW4IU6W?/,9\,-.%L81W^I@ZQO/&,0XQ=7)L7W*#99?ASD
MKAYM'-;Y-GW* IKVC'A=-O\/W[(?CVM+ ?7ER>M?K(LDKRFR>^\?P2O.5S
M_]2X1"&%Y)+>F5W=JG,BV9OY<%<Y48_.L\7_FF<>QS0=7YFHWD-)HOV.J:2;WNLO:[N!.
M.S(?CP\`5V;"N\0PSU#:XF@^:EJSG44T9GX/)<]Q)7ZJB"MV^UQ_WI<Y=W
MX9-.UJ9:OI_-7NNSZ4YNP[,>]$W_N50;& 5E]OO;S/]-Y7.][_R.8T=OOM
M3Y[W2LT=>6.?,\U1JGS-_AWPDMPM[XH?ZZ'/&M0<7?2H!4IXVJ^^^]<WEY$/
M[GC30K[;O]>GZ\>)2EKOM30UYOO#Y]+Z8OK&2FOHDS4K9;VQ>5BSUQ2S'C
M\[SI.[MQ64#_>\"C>#L)]#;@[V-D;T)PS_T8Y8`3*[HVSNM"SFN`T&GR[Z
M&3*XZ3^:F$!)\T"]"T'%.[\95+0B\[GULYJ@4\$8Y,$>C"NBX\ 8_#\?)$(/
M:T&D:,$A7(\(,(F7LCI$"R6T'!<L(JM$*@@,)[>\$VZ@Q!);S"+P3#,'3"
$@ ``.P``
`
end
Michael Sansom schrieb:
After a few more minutes of consideration, I don't see why Eagle
couldn't treat testpoints exactly the way they currently treat plated
holes. For instance, on the board I am currently working on, I have
four plated thru mounting hole. These holes are electrically tied to a
net (GND), and yet they appear nowhere on my schematic. They were added
during the PCB layout process and have nothing to do with the schematic.
Did you check if the files are still consistent?
Like testpoints, they are single port elements, i.e. they make one and
only one connection to a single net, so they do not interfere with the
functionality established by the schematic.
Clearly, Eagle already has a mechanism for handling single port elements
that are added to the PCB manually but not to the schematic. A
testpoint would simply be a similar element that consisted of a single
non-drilled pad.
I don't think that Eagle already has such a mechanism. For every
connected pad in the board, you need a pin in the schematic (more or
less visible, Warren already provided an example). And your ICTPs need
pads (normally small round SMDs on one of the outer layers), hence they
need pins in the schematic for a consistent connection.
BTW, it's good to see the testpoints in the schematic, too - and the
schematic designer can easily add them to all nets that shall be
accessible later (and leave the other nets without). Then, the
testpoints can also easily be considered during board layout and you
don't need a third person to add just the testpoints - without detailed
knowledge of the schematic and some layout details, this is somewhat
risky anyway.
Tilmann
Michael Sansom wrote on Tue, 28 December 2010 11:25
In any engineering company I've ever
participated in of even a moderate size, the insertion of test points
is
normally a post processing function, done by the PCB designer who more
often than not is not the engineer who generated the schematic.
That's a bad idea. If you have a separate person doing the layout (that
itself is usually not a good idea), then they are usually a draftsman and
not a electrical engineer. They can't look at the circuit and determine
which nets need to be brought out to be measured or driven externally
during board test. This process may include a separate production test
engineer, but should always include the circuit designer.
For example, many points connected to a microcontroller don't need to be
connected directly to the tester. Usually you set up a communication link
to the microcontroller and have it report on the state of signals or drive
them as required. With a little cleverness, you can infer the operation of
components between the external connections and the micro too sometimes.
The point is, you don't want to blindly connect a pogo pin pad (or whatever
you use to connect to the tester) to every net. That would add needless
complexity to the board, the tester, and the test process.
Since you have to think about where to connect test points, these should be
on the schematic. Someone will need to review the test plan, which will
include matching test point on the board with the schematic. For
troubleshooting you want to know what TP7, for example, is connected to.
Or often you have the reverse case where you want to put a scope probe on a
particular net and want to know if it has a test point, where it is on the
board, and how it's labeled. In other words, you want test points to show
up in the cross reference list just like any other component.
--
Web access to CadSoft support forums at www.eaglecentral.ca. Where the CadSoft EAGLE community meets.
On 12/29/2010 2:22 AM, Tilmann Reh wrote:
Michael Sansom schrieb:
>> After a few more minutes of consideration, I don't see why Eagle
>> couldn't treat testpoints exactly the way they currently treat plated
>> holes. For instance, on the board I am currently working on, I have
>> four plated thru mounting hole. These holes are electrically tied to a
>> net (GND), and yet they appear nowhere on my schematic. They were added
>> during the PCB layout process and have nothing to do with the schematic.
Did you check if the files are still consistent?
Yes, the files are still consistent. Why would they not be? Is this
not the way the add hole function works. It seems to work just like the
add via function as far as I can tell.
>> Like testpoints, they are single port elements, i.e. they make one and
>> only one connection to a single net, so they do not interfere with the
>> functionality established by the schematic.
>>
>> Clearly, Eagle already has a mechanism for handling single port elements
>> that are added to the PCB manually but not to the schematic. A
>> testpoint would simply be a similar element that consisted of a single
>> non-drilled pad.
I don't think that Eagle already has such a mechanism. For every
connected pad in the board, you need a pin in the schematic (more or
less visible, Warren already provided an example). And your ICTPs need
pads (normally small round SMDs on one of the outer layers), hence they
need pins in the schematic for a consistent connection.
Indeed Eagle must have such a mechanism. Do you have schematic elements
for all the vias on your PCB? What exactly is the difference between a
via and a test point from a schematic/layout consistency standpoint? An
ICT test point is simply a via without a drill through it.
BTW, it's good to see the testpoints in the schematic, too - and the
schematic designer can easily add them to all nets that shall be
accessible later (and leave the other nets without). Then, the
testpoints can also easily be considered during board layout and you
don't need a third person to add just the testpoints - without detailed
knowledge of the schematic and some layout details, this is somewhat
risky anyway.
Tilmann
You are telling me how you think adding test points should work. I'm
telling you how it does work in the vast majority of companies that I've
ever seen. I can say that fairly confidently based on the number of
companies that I have worked for as a hardware designer, and the far
greater number of schematics from different companies I have looked
at. It is very rare for the engineer to place test points on his
schematic for ICT testing (remember, for ICT ideally you want 100% of
nets to have test points). Generally, engineers will place test points
at signals of interest that he wants to probe with a scope or other
instrumentation for debug. Generally this will be a small fraction of
the total net count.
At all but the very smallest companies I've worked with, adding test
points for ICT is a post processing operation, in fact it's often not
done until the second or third prototype layout. As the layout
progresses, it is up to the hardware designer to look at high speed nets
to ensure that adding test points have not created any issues. In many
schematic capture/layout flows the hardware engineering will add some
sort of "no_test_point" attribute to critical high speed nets to inform
the pcb designer to not insert test points.
Do you really add test point components to all the nets on your schematic?
On 12/27/2010 05:35 PM, Michael Sansom wrote:
Is there a way to systematically insert ICT testpoints onto a PCB layout
without putting a testpoint component on each net on my schematic?
Ideally I'd like to know the percent of nets covered by testpoints and
have someway to highlight or locate nets without a testpoint so I can
either add one or can decide that the particular net isn't worth the
trouble to test.
-Michael
You could close the schematic, and then ADD the package for your
testpoint to the board, define an electrical connection with the SIGNAL
tool, and then route the test point with the ROUTE tool. When you next
open the schematic, Eagle will complain that the schematic and board are
not consistent, so you should only do this on a copy of your board---try
to integrate this with your version control system.
In order to verify that the test points cover all nets, you could use a
user-language program that will tell you the percentage covered and list
the nets that are not covered. If you can't find an uncovered net, you
can use the SHOW command to find it.
-Dave
On 12/29/2010 6:40 AM, Olin Lathrop wrote:
Michael Sansom wrote on Tue, 28 December 2010 11:25
>> In any engineering company I've ever participated in of even a
>> moderate size, the insertion of test points
>> is normally a post processing function, done by the PCB designer who more
>>
>> often than not is not the engineer who generated the schematic.
That's a bad idea. If you have a separate person doing the layout (that
itself is usually not a good idea), then they are usually a draftsman and
not a electrical engineer. They can't look at the circuit and determine
which nets need to be brought out to be measured or driven externally
during board test. This process may include a separate production test
engineer, but should always include the circuit designer.
Once again, you guys are telling me how you think the Schematic
Capture/PCB Layout flow should work. I'm telling you how it does
work based on the large number of companies I have worked for or
interfaced with. Not surprisingly, the work flow you propose meshes
well with what your tools support. But that is putting the cart before
the horse. You're asking the world to conform to your concept of the
work flow. I think you're putting blinders on yourself.
In fact, there are excellent reasons to have the hardware designer
capturing the schematic and the PCB designer doing the layout to be
different people. The required skill sets are not the same. A
hardware designer needs to understand how to cost effectively implement
some desired function in hardware. The PCB designer needs to understand
the intricacies of PCB fabrication and the automated PCB assembly
process (i.e. board loading, wave & reflow soldering, etc.). The PCB
designer needs to be able to optimize the layout for best PCB yield and
lowest assembly costs. In all but the simplest hardware/PCB designs the
best way to optimize these two functions it to get two people who are
highly skilled in their respective fields. It is much harder to find
people that are truly expert in hardware design, PCB fabrication, and
manufacturing. Besides that, having a separate hardware and PCB
designer will normally get the work done faster. If I lay out a PCB
every couple of months, my layout skills will not be as good as
someone who lays out PCBs every day. He will be both faster and
better than me at laying out PCBs.
Now, of course the hardware designer should occasionally look over the
shoulder of the PCB designer to be aware of what he is doing and he
definitely should inspect and approve the final layout.
For example, many points connected to a microcontroller don't need to be
connected directly to the tester. Usually you set up a communication link
to the microcontroller and have it report on the state of signals or drive
them as required. With a little cleverness, you can infer the operation of
components between the external connections and the micro too sometimes.
Simply not true. How will you determine if a microcontroller's pins are
soldered to the PCB if you don't have an in-circuit test point.
Normally, the way that is tested is you will connect the microcontroller
and any other JTAG compliant devices to a JTAG scan chain. Signals that
route between two JTAG capable devices can indeed be checked without a
test point. But what about signals that don't terminate on another JTAG
device? Say a signal originating on a microcontroller port pin that
ultimately connects to some analog circuit. How are you going to test
connectivity without a test point? Normally you would use the JTAG port
to command the port pin to go high and low then use your ICT tester to
observe the result.
The point is, you don't want to blindly connect a pogo pin pad (or whatever
you use to connect to the tester) to every net. That would add needless
complexity to the board, the tester, and the test process.
Maybe you don't want to do that, but I and many other companies do
exactly that, except we don't do it blindly. On signals that are low
speed, you can pretty much put a test point wherever you want. However,
I agree that on high speed signals you either want to place the test
point at a specific place or skip the test point altogether. The former
is done by having the hardware designer communication with the PCB
designer (either verbally or through notes on the schematic). The
latter is typically done by putting a "no_test_point" (or something
similar) attribute on the critical nets.
Since you have to think about where to connect test points, these should be
on the schematic. Someone will need to review the test plan, which will
include matching test point on the board with the schematic. For
troubleshooting you want to know what TP7, for example, is connected to.
Or often you have the reverse case where you want to put a scope probe on a
particular net and want to know if it has a test point, where it is on the
board, and how it's labeled. In other words, you want test points to show
up in the cross reference list just like any other component.
I do drop test points on the schematic on specific nets that I want to
make sure are covered so that I insure it is there and also get a
schematic reference designator. On the other hand, if I want to look at
a test point that is intended for ICT, I pull up the Gerber files or the
layout board files and find the ICT test point on the layout. It's not
that hard.
The work flow I've just described is the way a great many of medium
sized and larger companies do things. I agree, it's not the way a one
or two man shop may work. But even then, I've run small companies and
about half the time I hired a PCB designer as a subcontractor so even in
the case of a very small company (four people in this case) the
schematic capture and pcb layout functions were split. And I've seen
very very few schematic after 25 years as a hardware designer that had
all the ICT test points on the schematic (it just makes a mess if you've
got a complex schematic). I don't doubt that some people do this, but
it is rare in my experience (yours may vary). I've worked at
companies varying in size from ~2000 employees to 3 employees so far.
On 12/28/2010 4:02 PM, Warren Brayshaw wrote:
"Michael Sansom"<mssansom@hotmail.com> wrote in message
news:ifb4bo$pg7$1@cheetah.cadsoft.de...
>> Is there a way to systematically insert ICT testpoints onto a PCB layout
>> without putting a testpoint component on each net on my schematic?
>> Ideally I'd like to know the percent of nets covered by testpoints and
>> have someway to highlight or locate nets without a testpoint so I can
>> either add one or can decide that the particular net isn't worth the
>> trouble to test.
>>
>> -Michael
Hi Michael
Your requirements to reconcile net names with test pads and have a freely
placeable copper object in the layout editor would likely require a new
special object.
I imagine an object that is similar to the via, but un-drilled and only on
the top or bottom layer, would work to some degree.
What you are left with then is, like a via, only being able to determine if
one of these objects has a net name the same as a wire (routing). More code
is required to determine if they touch.
For now the following idea may be acceptable to you. Doing it this way you
will be able to get all the net name reporting you require, after a ULP is
written.
It does involve the schematic but visually there is only an increase in the
number of 'junction' dots displayed. I would expect that in most instances
you will use the junctions that are already drawn and occasionally have to
place one on a net wire.
The test points symbol is mostly on a new User layer which you only display
when needed.
The attached image shows what I mean.
Packages for these test points need placing in the layout editor but there
will be an airwire to assist.
Using Devices with multiple packages you can conveniently "Change Package"
in the board editor to lay down a differently sized test point that is more
appropriate for the available space.
If the test point needs to be away from a trace, this method lets you route
back to the trace as there is a valid net connected (airwire)
The 'Show' command displaying the complete net assists with choosing the
optimum place for the test point.
A ULP could now identify which nets do not attach to an element (your
various test point styles) with a nominated prefix.
One of the current assembly ULPs could provide the XY locations of the test
points and maybe their related net.
HTH
Warren
Thanks for your suggestion Warren. That is certainly an improvement in
my opinion to the cluttered schematic that would result from attaching
visible test point components to the schematic on the majority of the nets.
Yes, I agree that a special component like a via would be required. In
fact, if I could just specify a via with no drill that would work as a
kludge.
Once again, thanks for the suggestion.
-Michael
