Testpoints for ICT testers

"Michael Sansom"  wrote .

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

......Ideally I'd like to know the percent of nets covered by testpoints

and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

There have been a lot of discussion on  the placement of pads and the

validity of testing regimes but very little on the second part of the

question.

As I understand it, most of the points contacted during testing are regular

pads. Eagle does not have a way of flagging these pads with a test point

attribute. Hopefully this will arrive when 'pad stacks' are implemented.

So, how do you analyse the layout to determine if nets have  test points or

pads acting as testpoints or nothing suitable?

It maybe reasonable to give a library part an 'ICT-testpoint' attribute.

This would imply that any time it is used all its pins were useful for

machine probing. The format of the text value within  the attribute could

even exclude or include particular pins. Only this would not be acceptable

for parts under heatsinks, for example. To counter this an attribute applied

to the part on the board of  'Don't probe' could be used. Now a ULP could

provide a listing of nets to points, close to what you were asking.

I imagine something could be done with another ULP that copies these points

designated as testpoints, and that includes vias, to a user defined layer or

the tTest and bTest layers. A bright colour here may assist in confirming

testpoint locations before generating a file for the fixture maker.

Just some thoughts

Warren

"Michael Sansom"  wrote .

Is there a way to systematically insert ICT testpoints onto a PCB layout

without putting a testpoint component on each net on my schematic?

......Ideally I'd like to know the percent of nets covered by testpoints

and

have someway to highlight or locate nets without a testpoint so I can

either add one or can decide that the particular net isn't worth the

trouble to test.

There have been a lot of discussion on  the placement of pads and the

validity of testing regimes but very little on the second part of the

question.

As I understand it, most of the points contacted during testing are regular

pads. Eagle does not have a way of flagging these pads with a test point

attribute. Hopefully this will arrive when 'pad stacks' are implemented.

So, how do you analyse the layout to determine if nets have  test points or

pads acting as testpoints or nothing suitable?

It maybe reasonable to give a library part an 'ICT-testpoint' attribute.

This would imply that any time it is used all its pins were useful for

machine probing. The format of the text value within  the attribute could

even exclude or include particular pins. Only this would not be acceptable

for parts under heatsinks, for example. To counter this an attribute applied

to the part on the board of  'Don't probe' could be used. Now a ULP could

provide a listing of nets to points, close to what you were asking.

I imagine something could be done with another ULP that copies these points

designated as testpoints, and that includes vias, to a user defined layer or

the tTest and bTest layers. A bright colour here may assist in confirming

testpoint locations before generating a file for the fixture maker.

Just some thoughts

Warren

Warren Brayshaw schrieb:

There have been a lot of discussion on  the placement of pads and the

validity of testing regimes but very little on the second part of the

question.

 

As I understand it, most of the points contacted during testing are regular

pads.

To my knowledge, this is not true. Especially in high volume ICT,

testpoints always are separate SMD pads. This makes sure that these

areas are always free for the test needles and have a clean, smooth

surface. When using pads as test points, it is very difficult to get

reproducible contact - and the needles wear out much faster due to

horizontal forces.

So, how do you analyse the layout to determine if nets have  test points or

pads acting as testpoints or nothing suitable?

If there were special ICTP objects (as suggested), it would be no

problem to generate a list of covered and uncovered signals, including

statistics, with a small ULP.

Tilmann