How to create library part with thermal pad?

"Shareef Jalloq" <shareef@jalloq.co.uk> wrote in message

news:ikaurh$bid$1@cheetah.cadsoft.de...

Hi there,

 

>

I initially tried just marking a tStop region in the shape of the pad

hoping that if I just drew a polygon over it in the layout editor and hit

ratsnest, all would work out.  All I got was a polygon around the pad not

connected to it.

 

>

When you tried to make a polygon in the editor did you give it the net name?

On 2011-02-26 16:31:22 +0000, Doug said:

 

When you tried to make a polygon in the editor did you give it the net name?

When I created the library part, the package didn't have a name for the

thermal pad.  You can't assign a name to a polygon in the library

package editor which was my problem.  You can do that with a pad, but

the pad can only be rectangular and not the T shape that is required.

Thanks.

Am 26.02.2011 14:22, schrieb Shareef Jalloq:

Hi there,

 

I was hoping someone could give me the recommended flow for creating a

library package with a thermal pad. I'm using an LME49600TS/NOPBLME49600TS/NOPB which has 5

pins and a thermal pad. The pad is electrically connected internally to

Vee.

 

I initially tried just marking a tStop region in the shape of the pad

hoping that if I just drew a polygon over it in the layout editor and

hit ratsnest, all would work out. All I got was a polygon around the pad

not connected to it.

 

I then tried to draw a polygon in the package and name it something but

I discovered you can't name polygons. A square pad would work I guess

but this isn't the shape of the pad which is in the shape of a 'T'.

 

Any pointers on the correct way of doing this? The demo board doesn't

have the pad polygon connected to the Vee pin so that shouldn't be an

issue.

 

Thanks, Shareef.

 

Attached the device as example.

Set in DRC menu | Clearance | Same Signals | SMD - SMD  to 0.0mm.

Mit freundlichen Grüßen / Best regards

Alfred Zaffran

--

_____________________________________________________________

Alfred Zaffran              Support

CadSoft Computer GmbH       Hotline:   08635-698930

Pleidolfweg 15              FAX:       08635-698940

84568 Pleiskirchen          eMail: <alf@cadsoft.de>

                             Web:   <www.cadsoft.de>

Registergericht: Amtsgericht Traunstein HRB 5573

Geschäftsführer: Dipl.-Ing. Klaus Schmidinger, Bodo Badnowitz

_____________________________________________________________

On 2011-02-28 07:48:11 +0000, A. Zaffran said:

Attached the device as example.

Set in DRC menu | Clearance | Same Signals | SMD - SMD  to 0.0mm.

 

 

Alfred Zaffran

Thanks a lot.

I am also having this problem. I cannot name my polygon to the name I want!

If I try to do this, the end result is the dialog window where you write

the name just dissappears after you click on the polygon edge, and the

polygon remains the same. It's very strange in the layout editor, I can

name my polygo whatever I need, but in the component editor, it simply

ignores my NAME request!

In modern lingo : What's up with that y'all?

or eighties version: Bummer dude, this polygon is having, like, an identity

crisis, or like, identiphobia?

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Redcutlass wrote on Tue, 29 March 2011 13:13

but in the component editor, it simply ignores my NAME request!

I think you mean the package editor?

It would be nice if you could draw arbitrary stuff and have that be part of

a pad such that the DRC doesn't create a flood of errors.  However, you

can't.  Any time you want a connection point you have to start with a pad.

You can then add copper to it as you like.  That will result in the right

copper, but the DRC will give you lots of overlap errors.

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Olin wrote on Tue, 29 March 2011 13:46

Redcutlass wrote on Tue, 29 March 2011 13:13

but in the component editor, it simply ignores my NAME request!

 

I think you mean the package editor?

 

That will result in the right copper, but the DRC will give you lots

of overlap errors.

Yes, sorry, I meant package editor.

Actually that seems to be exactly the problem: Even if I place a pad, the

copper ploygon I place around it, to mold to the shape I desire, does not

"connect" to the polygon. I wish I could explain it better... When I fill

my layout with ratsnest, it just goes all over the GND area, totally

ignoring the tStop layer I made for it. IsnT' that what the tStop (or

bStop) layer does? At least, that's how the SMD pads are treated...

thanks!

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Redcutlass wrote on Tue, 29 March 2011 15:42

Actually that seems to be exactly the problem: Even if I place a pad,

the copper ploygon I place around it,

That makes no sense.  If you place another copper polygon completely over a

pad, of course you won't get thermals.  The pad itself will generate copper

gaps for the thermals, but your explicit polygon will put copper there

anyway.

Quote:

IsnT' that what the tStop (or bStop) layer does?

It's not clear what you think they are supposed to do.  The layers are well

documented in the help.  Things drawn in the tStop and bStop layers make

holes in the top and bottom solder mask, respectively.  I can't even guess

why you think this has anything to do with thermals.  You really need to

read the help for layers.

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Actually I don't understand why you say it generates holes...

I might need to read the help section on tStop, but I know that there were

no holes generated in our boards on the tStop layer...

I looked in the pdf Manual and they donT' mention much detail about the t

and b Stop layers...

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

On 3/29/2011 3:10 PM, Owen wrote:

Actually I don't understand why you say it generates holes...

I might need to read the help section on tStop, but I know that there were

no holes generated in our boards on the tStop layer...

 

I looked in the pdf Manual and they donT' mention much detail about the t

and b Stop layers...

maybe you are confusing *Stop ( negative solder mask) with *Restrict (

negative copper in fills) ???