I have a 4-layer board originally routed in Eagle V4 (Linux/Pro) that passed
ERC/DRC and went to production. It was discovered later that a connector had
issues (shorts) with vias under it. I'm now correcting that in V5.11.0
(Linux/Pro). I edited the connector symbol to include a vRestrict layer and
did a Library-Update All. The connector updated correctly and the vRestrict
layer now shows up as expected. Curiously, though, when I run DRC no errors
are flagged, even though nothing on the board changed except the connector
and the vias are still there, now clearly underneath the vRestrict layer.
I did a newsgroup search and the only possibility I saw was an issue with
blind vias. My stackup, however, is a simple (18+916) with no blind vias
defined. Is there some other setting I might be missing, or have I just run
into an Eagle bug?


