How to clip silk layers using the stop mask layer?

alank2 schrieb:

In this picture you can see that I have a folded over PTC and its

silkscreen runs over a couple of pads:

http://home.earthlink.net/~alank2/f1.png[/img]

It's pretty common that the silkscreen runs over surface that is

intended to be blank - maybe pads or vias.

I know I could go into the library, make a custom package and copy

the existing package and modify it to remove the silkscreen where it

runs into the pads, but I wouldn't want to do this each and everytime

I run into a situation like this.  I might end up with 20 packages

for a single one with various silk screen parts missing because of

different projects.

 

Is there a way that CAM job could do this automatically on its gerber

output?  Is there another way to do this?

Normally, you don't need to care about this at all, since the board

house will automatically mask the silkscreen with the solder stop mask

to avoid printing on solderable surfaces. This is common practice.

If you're not sure, talk to them before ordering your boards.

Tilmann

Hi,

I am surprised that Eagle has a drc error for this, but no way to correct it.  Wouldn't it be better to fix it in your board design instead of relying on a board house to fix it?

Thanks,

Alan

alank2 schrieb:

I am surprised that Eagle has a drc error for this,

IMHO, that should be rather a warning... BTW, if you don't display the

stop mask layers during DRC, it won't show these "errors".

but no way to

correct it.  Wouldn't it be better to fix it in your board design

instead of relying on a board house to fix it?

It can't be "fixed" in the design. Just think about the vias, their

position can always collide with the silkscreen of a part. The only way

to fix this would be in the CAMP (masking the silkscreen with the stop

mask). This has already been suggested, but not implemented - I think

other issues are (much) more urgent...

And, the board houses are used to do this, I /never/ had any problems

with silkscreen on solderable surfaces. So it's more a flaw, not really

erroneous data.

Tilmann

"alank2" <communitymanager@premierfarnell.com> wrote in message

news:53145953.691300666029901.JavaMail.jive@flcspu-csapp-01.premierfarnell.com...

I am surprised that Eagle has a drc error for this, but no way to correct

it. Wouldn't it be better to fix it in your board design instead of

relying on a board house to fix it?

It is very logic that it does have a drc. The reason for having silk is to

be able to read it. If its on a pad and need to be masked, the usefulness is

lost and you may just as well skip the silk all together (as I usually do).

I'm pretty sure silk is mostly useful for low density boards with through

hole components. For high density and smd components it makes more problems

that it solves. You may end up with silk under a smd component that prevents

it from lying flat on the pcb, leaving bad soldering spots or tombstoning

effects.