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High Current Traces

e14 Contributor

Hi,

 

I'm a new Eagle user, but I suspect this is actually a more complicated question.

 

I have traces that will carry up to 2 amps.  Those traces also control various FETs and other signals.  If I set that net node to the trace width for the high current, all of the net gets set to that width and I don't have room to route my board.  I've already re-arranged all my components so that the wide traces are short and the pins near each other.  I've even gone from 4 layers to 6 layers.  (The board routes just fine with 4 layers by 7 mil traces.)

 

I don't see a way to set the width of signals before routing, and after routing is too late.  One idea is to isolate the low current part of the net from the high current with a 0 ohm resistor, then after routing fill in will a trace.  But even that seems a little clumsy.

 

I'm considering going to thicker copper layers so that I can reduce the trace width, but I haven't tried that yet.

 

Does anyone have any ideas on how I might solve this problem?

 

Thanks,

 

Dave

Parents

  • Thanks to everyone.  I was able to finish this up.

     

    I didn't want to disable thermals because the one pad would be way too

    large.  But with some tweaking I was able to get the polygon where I wanted

    it.  I did need to set the width of the polygon to a lower value than the

    net class.  This gives me a width error but the polygon covers the set of

    pads so that's OK.

     

    I also have to route one signal level trace in the high current net class

    manually with a thinner trace so that I don't have clearance errors to the

    adjacent pins.  Again, I know what this is and the thinner trace is OK

    here.

     

    So, after much head scratching, gerbers are done and will go out for fab.

     

    Thanks again for the help.

     

    Dave

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

Reply

  • Thanks to everyone.  I was able to finish this up.

     

    I didn't want to disable thermals because the one pad would be way too

    large.  But with some tweaking I was able to get the polygon where I wanted

    it.  I did need to set the width of the polygon to a lower value than the

    net class.  This gives me a width error but the polygon covers the set of

    pads so that's OK.

     

    I also have to route one signal level trace in the high current net class

    manually with a thinner trace so that I don't have clearance errors to the

    adjacent pins.  Again, I know what this is and the thinner trace is OK

    here.

     

    So, after much head scratching, gerbers are done and will go out for fab.

     

    Thanks again for the help.

     

    Dave

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

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