High Current Traces

Hi

One option you may consider is to add a generous amount of solder on the tracks connecting the pads in case you feel you dont have a proper routing width.

Best wishes

Thanks to everyone.  I was able to finish this up.

I didn't want to disable thermals because the one pad would be way too

large.  But with some tweaking I was able to get the polygon where I wanted

it.  I did need to set the width of the polygon to a lower value than the

net class.  This gives me a width error but the polygon covers the set of

pads so that's OK.

I also have to route one signal level trace in the high current net class

manually with a thinner trace so that I don't have clearance errors to the

adjacent pins.  Again, I know what this is and the thinner trace is OK

here.

So, after much head scratching, gerbers are done and will go out for fab.

Thanks again for the help.

Dave

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Try disabling thermal of your polygons and ratsnest before autorouting?

How frustrating...  OK, so now I can post here, but it appears the file

size limit is only 51K.  At that size, my picture doesn't have enough

resolutions.

Here's a link to the picture:

http://www.davewillsinc.com/_Eagle/board.jpg

Thanks,

Dave

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Registered, but still cannot post a day later.

d.

Dave Wills wrote:

Guest wrote:

>

> On 6/14/2012 3:03 PM, Dave Wills wrote:

>> Sorry, I just keep running into roadblocks on this. There are 2

>> pictures of my board below, one after routing and one before

>> routing. The numbered squares are the pin numbers for the IC, 9

>> through 19 (10 left out).

>>

>> Pin 9 is on a wider net class (0.38 mm) than default 0.10 mm. The

>> pin width is only 0.25 mm and so pin 9 can't be routed

>> automatically. But since pin 9 is not a high current signal, I can

>> routed it manually with a 0.25 mm trace and that works fine. The

>> trace is shown as E in the top picture. It goes up, then left to pad

>> A.

>>

>> A and C are pads of capacitors and D is the pad of an inductor. B is

>> all that is left of the polygon I inserted. If you look at the

>> bottom picture you see the polygon extends all the way from A to D,

>> and is 0.38 mm wide so I don't get a width violation. Even so, when

>> adding in the width of the polygon all is contained within the area

>> I want to cover. The polygon is solid, but it looks like the router

>> trimmed it down. I don't want it trimmed down.

>>

>> F and H are parts of the next polygon below. The pins and polygon

>> are on a net class of 0.50 mm. This polygon covers pins 11 through

>> 16, around the corner of the IC and inductor pad G. Again, you can

>> see the polygon unrouted in the bottom picture. There are 2 bad

>> things about this. First, even though I've positioned the polygon so

>> it does not extend outside of the pins (bottom picture), the router

>> added wires between pins 11 and 12, and 15 and 16. These are the

>> bulges I mentioned in previous posts and you can see the clearance

>> warnings. I think I can get rid of these by changing the wire size

>> after routing, as long as the polygon covers the pins. Next, the

>> router trimmed my polygon which extended from pad G all the way to

>> the bottom of pin 16. And even though F, G and H are all within the

>> polygon, as is the via next to H, the router says the connection to

>> pad G is not routed. ???

>>

>> The polygon from pins 17, 18 and 19 has similar issues. The polygon

>> has been trimmed. The net class here is 0.38 mm, but it's still

>> weird that when the router connected pins 17 and 18 that it didn't

>> bulge towards pin 16. Same with pin 19. (Again, the pins are 0.25 mm

>> wide.)

>>

>> So those are the details. Questions are included above, but for

>> simplicity:

>>

>> - Why are the polygons trimmed?

>>

>> - I can change wire size to prevent the bulges on the pins, but that

>> works only if the polygons are not trimmed. How do I fix this?

>>

>> - Why is the one trace unrouted even though the 6 pins, the inductor

>> pad, the polygon and the via all have the same name?

>>

>> Thanks for taking a look.

>>

>> Dave

>>

>> Image:board.png

>>

>

> Your pictures did not make it to the newgroup or to eaglecentral.ca

>

> Jim

>

>

Hmmm... I see it just fine in the post. Maybe you're having problem

with the .png. Here's a .jpg.

 

Thanks,

 

Dave

 

Image:board.jpg

No Dave

The problem is you are using the Element14 site and that has always been

broken. Images don't get through. Attachments can get through but only if

you  do them a particular way.

It's a "Johnny come lately" that was not implemented well.

If you prefer a web access to the to the support forums it is recommended

you use eaglecentral

http://www.eaglecentral.ca/forums/

Only downside there is getting approved , but that's only a day. Searching

for old posts is great there.

Both these web portals are front ends to the master newsgroup forum

repository at

new.cadsoft.de

Get a newsreader set up, it's just like dealing with emails

HTH

Warren

--

Viewed / responded via the newsgroup at

news.cadsoft.de

Guest wrote:

 

On 6/14/2012 3:03 PM, Dave Wills wrote:

Sorry, I just keep running into roadblocks on this.  There are 2 pictures of my board below, one after routing and one before routing.  The numbered squares are the pin numbers for the IC, 9 through 19 (10 left out).

 

Pin 9 is on a wider net class (0.38 mm) than default  0.10 mm.  The pin width is only 0.25 mm and so pin 9 can't be routed automatically.  But since pin 9 is not a high current signal, I can routed it manually with a 0.25 mm trace and that works fine.  The trace is shown as E in the top picture.  It goes up, then left to pad A.

 

A and C are pads of capacitors and D is the pad of an inductor.  B is all that is left of the polygon I inserted.  If you look at the bottom picture you see the polygon extends all the way from A to D, and is 0.38 mm wide so I don't get a width violation.  Even so, when adding in the width of the polygon all is contained within the area I want to cover.  The polygon is solid, but it looks like the router trimmed it down.  I don't want it trimmed down.

 

F and H are parts of the next polygon below.  The pins and polygon are on a net class of 0.50 mm.  This polygon covers pins 11 through 16, around the corner of the IC and inductor pad G.  Again, you can see the polygon unrouted in the bottom picture.  There are 2 bad things about this.  First, even though I've positioned the polygon so it does not extend outside of the pins (bottom picture), the router added wires between pins 11 and 12, and 15 and 16.  These are the bulges I mentioned in previous posts and you can see the clearance warnings.  I think I can get rid of these by changing the wire size after routing, as long as the polygon covers the pins.  Next, the router trimmed my polygon which extended from pad G all the way to the bottom of pin 16.  And even though F, G and H are all within the polygon, as is the via next to H, the router says the connection to pad G is not routed.  ???

 

The polygon from pins 17, 18 and 19 has similar issues.  The polygon has been trimmed.  The net class here is 0.38 mm, but it's still weird that when the router connected pins 17 and 18 that it didn't bulge towards pin 16.  Same with pin 19.  (Again, the pins are 0.25 mm wide.)

 

So those are the details.  Questions are included above, but for simplicity:

 

- Why are the polygons trimmed?

 

- I can change wire size to prevent the bulges on the pins, but that works only if the polygons are not trimmed.  How do I fix this?

 

- Why is the one trace unrouted even though the 6 pins, the inductor pad, the polygon and the via all have the same name?

 

Thanks for taking a look.

 

Dave

 

  Image:board.png

 

 

Your pictures did not make it to the newgroup or to eaglecentral.ca

 

Jim

 

 

Hmmm...  I see it just fine in the post.  Maybe you're having problem with the .png.  Here's a .jpg.

Thanks,

Dave

On 6/14/2012 3:03 PM, Dave Wills wrote:

Sorry, I just keep running into roadblocks on this.  There are 2 pictures of my board below, one after routing and one before routing.  The numbered squares are the pin numbers for the IC, 9 through 19 (10 left out).

 

Pin 9 is on a wider net class (0.38 mm) than default  0.10 mm.  The pin width is only 0.25 mm and so pin 9 can't be routed automatically.  But since pin 9 is not a high current signal, I can routed it manually with a 0.25 mm trace and that works fine.  The trace is shown as E in the top picture.  It goes up, then left to pad A.

 

A and C are pads of capacitors and D is the pad of an inductor.  B is all that is left of the polygon I inserted.  If you look at the bottom picture you see the polygon extends all the way from A to D, and is 0.38 mm wide so I don't get a width violation.  Even so, when adding in the width of the polygon all is contained within the area I want to cover.  The polygon is solid, but it looks like the router trimmed it down.  I don't want it trimmed down.

 

F and H are parts of the next polygon below.  The pins and polygon are on a net class of 0.50 mm.  This polygon covers pins 11 through 16, around the corner of the IC and inductor pad G.  Again, you can see the polygon unrouted in the bottom picture.  There are 2 bad things about this.  First, even though I've positioned the polygon so it does not extend outside of the pins (bottom picture), the router added wires between pins 11 and 12, and 15 and 16.  These are the bulges I mentioned in previous posts and you can see the clearance warnings.  I think I can get rid of these by changing the wire size after routing, as long as the polygon covers the pins.  Next, the router trimmed my polygon which extended from pad G all the way to the bottom of pin 16.  And even though F, G and H are all within the polygon, as is the via next to H, the router says the connection to pad G is not routed.  ???

 

The polygon from pins 17, 18 and 19 has similar issues.  The polygon has been trimmed.  The net class here is 0.38 mm, but it's still weird that when the router connected pins 17 and 18 that it didn't bulge towards pin 16.  Same with pin 19.  (Again, the pins are 0.25 mm wide.)

 

So those are the details.  Questions are included above, but for simplicity:

 

- Why are the polygons trimmed?

 

- I can change wire size to prevent the bulges on the pins, but that works only if the polygons are not trimmed.  How do I fix this?

 

- Why is the one trace unrouted even though the 6 pins, the inductor pad, the polygon and the via all have the same name?

 

Thanks for taking a look.

 

Dave

 

  Image:board.png

 

Your pictures did not make it to the newgroup or to eaglecentral.ca

Jim

Sorry, I just keep running into roadblocks on this.  There are 2 pictures of my board below, one after routing and one before routing.  The numbered squares are the pin numbers for the IC, 9 through 19 (10 left out).

Pin 9 is on a wider net class (0.38 mm) than default  0.10 mm.  The pin width is only 0.25 mm and so pin 9 can't be routed automatically.  But since pin 9 is not a high current signal, I can route it manually with a 0.25 mm trace and that works fine.  The trace is shown as E in the top picture.  It goes up, then left to pad A.

A and C are pads of capacitors and D is the pad of an inductor.  B is all that is left of the polygon I inserted.  If you look at the bottom picture you see the polygon extends all the way from A to D, and is 0.38 mm wide so I don't get a width violation.  Even so, when adding in the width of the polygon all is contained within the area I want to cover.  The polygon is solid, but it looks like the router trimmed it down.  I don't want it trimmed down.

F and H are parts of the next polygon below.  The pins and polygon are on a net class of 0.50 mm.  This polygon covers pins 11 through 16, around the corner of the IC and inductor pad G.  Again, you can see the polygon unrouted in the bottom picture.  There are 2 bad things about this.  First, even though I've positioned the polygon so it does not extend outside of the pins (bottom picture), the router added wires between pins 11 and 12, and 15 and 16.  These are the bulges I mentioned in previous posts and you can see the clearance warnings.  I think I can get rid of these by changing the wire size after routing, as long as the polygon covers the pins.  Next, the router trimmed my polygon which extended from pad G all the way to the bottom of pin 16.  And even though F, G and H are all within the polygon, as is the via next to H, the router says the connection to pad G is not routed.  ???

The polygon from pins 17, 18 and 19 has similar issues.  The polygon has been trimmed.  The net class here is 0.38 mm, but it's still weird that when the router connected pins 17 and 18 that it didn't bulge towards pin 16.  Same with pin 19.  (Again, the pins are 0.25 mm wide.)

So those are the details.  Questions are included above, but for simplicity:

- Why are the polygons trimmed?

- I can change wire size to prevent the bulges on the pins, but that works only if the polygons are not trimmed.  How do I fix this?

- Why is the one trace unrouted even though the 6 pins, the inductor pad, the polygon and the via all have the same name?

Thanks for taking a look.

Dave

I think I've fixed it.  What I did was to let the auto router route the wires, then change the wire width to something really small.  This reduces the extension of the formerly 0.50 mm wire outside of the pin to something really small.  And since the 0.25 mm pin is overlaid with a polygon, that shouldn't be a problem.  I do get width errors, but I think these are OK because of the polygon.

But in order to prevent the polygon from encroaching on the next pin, I've made the polygon width really small (0.01 mm).  That gives me width errors too.

Since the polygon is filled, the width errors should be OK, right?

Thanks to all for the help.

Dave