Newbie: EAGLE CAD Errors

Usman Ali wrote:

hello,

i received the land patter of a  LC4 package from a friend of

mine...also took the design rule limitation from my fabrication

house. I applied the DRC for this package and faced these three type

of errors.. have a look at attached picture.

can any one suggest where these problems comes from.. and how to

resolve this issue.

It's difficult to assist using just the provided image. Attatching the

design .brd file would enable exact answers to be given by someone using v6

as they would be abl eto deconstruct the method you have used

So some educated guesses follow.

All the errors on the lower edge of the board appear to arise from the

package being placed to near to the edge of the board. I suspect the

smd pads of the package are triggering the DRC error. The DRC setting to

review is   DRC>Distance>Copper Dimension

For a test, reduce the setting to a few mil and see if those errors do not

occur on the next DRC check.

Next you need to isolate the errors at the  three tapering traces know their

types.

I would endeavour to find the reasons for the errors around one tapering

trace. The fix for those errors will rid you of the errors for the other two

tapering traces. So, approve all the errors except those in the area of the

tapering trace you choose to troubleshoot.

I suspect you may not have ROUTEd the segments with reducing width but

placed wires

Purhaps  you did not generate this board from the schematic editor but built

the board by itselft and and have not got the signal names matching.

The clearance of your net classes may be conflicting with your DRC

clearances so review those.

Warren

Usman Ali wrote:

hello,

i received the land patter of a  LC4 package from a friend of

mine...also took the design rule limitation from my fabrication

house. I applied the DRC for this package and faced these three type

of errors.. have a look at attached picture.

can any one suggest where these problems comes from.. and how to

resolve this issue.

It's difficult to assist using just the provided image. Attatching the

design .brd file would enable exact answers to be given by someone using v6

as they would be abl eto deconstruct the method you have used

So some educated guesses follow.

All the errors on the lower edge of the board appear to arise from the

package being placed to near to the edge of the board. I suspect the

smd pads of the package are triggering the DRC error. The DRC setting to

review is   DRC>Distance>Copper Dimension

For a test, reduce the setting to a few mil and see if those errors do not

occur on the next DRC check.

Next you need to isolate the errors at the  three tapering traces know their

types.

I would endeavour to find the reasons for the errors around one tapering

trace. The fix for those errors will rid you of the errors for the other two

tapering traces. So, approve all the errors except those in the area of the

tapering trace you choose to troubleshoot.

I suspect you may not have ROUTEd the segments with reducing width but

placed wires

Purhaps  you did not generate this board from the schematic editor but built

the board by itselft and and have not got the signal names matching.

The clearance of your net classes may be conflicting with your DRC

clearances so review those.

Warren

I appriciate ur suggestions,

yes ofcourse lowering the value removes the errors but i was wondering if

ignoring the errors will affect the manufacturing process or not e.g

dimension error or clearance error.

also the board is produced from schematics, vias are placed manualy but

named the same as 'gnd', polygon for tapering is also named the same as

signal name for every signal and drawn with the same line width as the pad

size...

for better look i have attached both .brd and .sch file to the thread

http://wikisend.com/download/134390/HMC144LC4.zip

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