Using internal layers effectively

Andrew Forrest schrieb:

  I'm using a 4 layer board with SMDs mounted on one side only. The

auto-router is only getting about 85% of the connections, there are

about 550 total. However there are only about a dozen tracks on the

internal layers. I am using layers setup (12+316) for pcb-pool.

 

The problem seems to centre around a LQFP100 package that does not have

space to allow tracks between pins, however this only prevents a two

layer design. I have tried reducing the costs of internal layers and

reducing the costs of vias, but these do not end up having much effect.

Am I missing some strategy for using internal layers more effectively?

First of all, a good parts placement is essential. Every hour you spend

on the placement, you will save twice during layout.

Second, autorouting will never provide really good results - especially

in areas of higher density like around your LQFP100 device. Route this

part manually, before eventually using the autorouter for the rest.

(My designs are 100% manually routed.)

Third, a common ML4 design strategy is to use the inner layers only for

ground and supply voltages. All signal routing is done on the outer

layers only. If you have placed your parts properly (see 1), you'll be

able to route about 90-95% of your signals on the top layer (and the

remaining 5-10% on the bottom layer). Take care that you have ground and

supply layers, so you can exclude all supplies from ratsnest and don't

let them confuse you during layout and optimization. Later, include

ground and supplies in ratsnest again and add the needed connections as

short stubs with vias into the planes.

Tilmann

Andrew Forrest schrieb:

  I'm using a 4 layer board with SMDs mounted on one side only. The

auto-router is only getting about 85% of the connections, there are

about 550 total. However there are only about a dozen tracks on the

internal layers. I am using layers setup (12+316) for pcb-pool.

 

The problem seems to centre around a LQFP100 package that does not have

space to allow tracks between pins, however this only prevents a two

layer design. I have tried reducing the costs of internal layers and

reducing the costs of vias, but these do not end up having much effect.

Am I missing some strategy for using internal layers more effectively?

First of all, a good parts placement is essential. Every hour you spend

on the placement, you will save twice during layout.

Second, autorouting will never provide really good results - especially

in areas of higher density like around your LQFP100 device. Route this

part manually, before eventually using the autorouter for the rest.

(My designs are 100% manually routed.)

Third, a common ML4 design strategy is to use the inner layers only for

ground and supply voltages. All signal routing is done on the outer

layers only. If you have placed your parts properly (see 1), you'll be

able to route about 90-95% of your signals on the top layer (and the

remaining 5-10% on the bottom layer). Take care that you have ground and

supply layers, so you can exclude all supplies from ratsnest and don't

let them confuse you during layout and optimization. Later, include

ground and supplies in ratsnest again and add the needed connections as

short stubs with vias into the planes.

Tilmann