Via diameter size control

Bob Starr wrote:

The global sizing of via diameters in the DRC just doesn't cut it for

hi-tech BGA stuff. We need a way to override the DRC for both under

and over the DRC limit vias. Once you move to high density fine pitch

BGA's, via size control becomes a real problem.

 

I understand how "auto" via size parameter works, but for things like

"via in pad" and "micro vias" and stacked micro vias, the current

implementation for controlling via diameters is just not suitable.

 

While the global DRC auto size and parameters works for the majority

of vias on a board, often I need to specify smaller annular rings in

the BGA field than I would from all other vias on the board.

 

Sure, I could set the DRC parameter to smallest ring I need in the BGA

area, but then I'd have to manually specify the diameter of every

other via outside my BGA area as larger - what a pain!

 

The via size parameter needs to fully respect the value given if the

diameter specified is not auto and smaller than the DRC limit. Maybe

the diameter could be specified negative or something, but we need a

way to override this "auto" minimum size feature.

 

This has been killing me for a long time and causes great pains

routing these high density BGA's. Please give use a way to control

the via diameters completely at the via level!

 

Bob

I agree.

There are other inate Eagle features that are now impacted by  the scale of

the modern componentry. They have been highlighted over the months.

A similar issue to Bob's request, and needs to be addressed at the same

time,  is  the ability to specify a hole that the copper does not stay clear

of.

A raw 'Drill' that can be part of a package or placed on the Board.

Said another way, a Hole that is not reflected in the Dimension layer but is

in the Drill layer.

Warren

--

Viewed / responded via the newsgroup at

news.cadsoft.de

Bob Starr wrote:

The global sizing of via diameters in the DRC just doesn't cut it for

hi-tech BGA stuff. We need a way to override the DRC for both under

and over the DRC limit vias. Once you move to high density fine pitch

BGA's, via size control becomes a real problem.

 

I understand how "auto" via size parameter works, but for things like

"via in pad" and "micro vias" and stacked micro vias, the current

implementation for controlling via diameters is just not suitable.

 

While the global DRC auto size and parameters works for the majority

of vias on a board, often I need to specify smaller annular rings in

the BGA field than I would from all other vias on the board.

 

Sure, I could set the DRC parameter to smallest ring I need in the BGA

area, but then I'd have to manually specify the diameter of every

other via outside my BGA area as larger - what a pain!

 

The via size parameter needs to fully respect the value given if the

diameter specified is not auto and smaller than the DRC limit. Maybe

the diameter could be specified negative or something, but we need a

way to override this "auto" minimum size feature.

 

This has been killing me for a long time and causes great pains

routing these high density BGA's. Please give use a way to control

the via diameters completely at the via level!

 

Bob

I agree.

There are other inate Eagle features that are now impacted by  the scale of

the modern componentry. They have been highlighted over the months.

A similar issue to Bob's request, and needs to be addressed at the same

time,  is  the ability to specify a hole that the copper does not stay clear

of.

A raw 'Drill' that can be part of a package or placed on the Board.

Said another way, a Hole that is not reflected in the Dimension layer but is

in the Drill layer.

Warren

--

Viewed / responded via the newsgroup at

news.cadsoft.de