Generate schematic automatically from FPGA pi nout?

autodeskguest over 11 years ago

Hi,

I used to create FPGA schematic manually but my last project has a 1500pins

FPGA and I would like to automate things to avoid errors and also save some

time.

I am a beginner in ULP scripts so I would appreciate some advice.

I didn't find any way to automate passing from FPGA pinout in (Quartus .qsf

file for example) to board schematic.

I have this procedure in mind:

- create FPGA symbol/package with "make-symbol-device-package-bsdl.ulp"

(already done)

- add a FPGA part on a schematic sheet

Then an ulp script has to:

- Parse Altera pinout file (qsf) to extract signal and pin names

- For each fpga symbol pin mentioned in the FPGA pinout file:

=> Trace and connect a wire to the fpga symbol pin

=> Label this wire with the signal name from .qsf file and display the

name

Example:

set_location_assignment PIN_A7 -to sensor_clk (from fpga pinout file)

This statement leads to the creation a wire named "sensor_clk" connected to

fpga pin A7.

Is it possible to do something like that?

I really didn't know how to start. I gave a look at "cmd-net-list2sch.ulp"

script but I can't make it work for a bga component.

Thanks in advance for helping.

Web access to CadSoft support forums at www.eaglecentral.ca. Where the CadSoft EAGLE community meets.

Parents

autodeskguest over 11 years ago
gg <gendreau@optronis.com> wrote:
...
Example:
set_location_assignment PIN_A7 -to sensor_clk (from fpga pinout file)
This statement leads to the creation a wire named "sensor_clk" connected to
fpga pin A7.

Is it possible to do something like that?
I really didn't know how to start. I gave a look at "cmd-net-list2sch.ulp"
script but I can't make it work for a bga component.

So you let the FPGA tool choose the pins and you design the PCB after
routing the FPGA?

I do it the other way round. I design the board and give the choosen FPGA
pins as constraints to the FPGA placement. The constraint list is generated
form the eagle netlist with appended perl script. It is tested for
xilinx. Quicklogic is probably bit-rotten with time.

Bye
--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
-
Tel. 06151 162516 -
Fax. 06151 164321 -
#!/usr/bin/perl

Take a eagle board netlist and search for connections to a part. Exclude
selected nets,

Copyright Uwe Bonnes, 2002-2010 bon@elektron.ikp.physik.tu-darmstadt.de

net2ucf -h [excludepattern[s]]

This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Public License for more details.

if ((!@ARGV) ||($ARGV[0] eq "-h"))
{
    print "Usage: $0 -h ...\n";
    print "\t-h: print this help\n";
    print "\t-l: write netnames as lowercase\n";
    print "\t-v: verbose progress indication on stdout\n";
    print "\t-n: ignore stubs (Net named as pad)\n";
    print "\t[netlist]: a netlist exported from the Cadsoft Eagle Package\n";
    print "\t[format]= quicklogic|xilinx \n";
    print "\t[partdescriptor]: The name of the part to look for, e.g. \"IC1\"\n";
    print "\t[excludepattern] may be a regular expression\n";
    print "\te.g. $0 -i nets xilinx ic1 \"GND.\" \"VCC.\" \"JTAG_.*\"\n";
    print "\tOutput is written to {netlist].[pcf|ucf]\n";
    print "\tArguments are case sensitive\n";
    print "\tCheck resulting files!\n";
    exit 0;
}

@SAVEARGS= @ARGV;

while ($_ = $ARGV[0], /^-/)
{
    shift;
    last if /^--$/;
    if (/^-l(.*)/)
    {
     $lowercase = 1;
    }
    if (/^-v(.*)/)
    {
     $verbose = 1;
    }
    if (/^-n(.*)/)
    {
     $no_stubs = 1;
    }
}

if ($verbose)
{
    if ($lowercase)
    {
     print "Lowercase set\n";
    }
    else
    {
     print "Lowercase not set\n";
    }
    print "Verboseset\n";
}

if (!open (TXT, $ARGV[0] ))
{
    open (TXT, $ARGV[0] . ".net") or die "Unable to open $ARGV[0] and $ARGV[0].net!\n";
}

treat cr/lf:
$/ = "\r\n";
undef $/;
$_ = xilinx.ucf") or die "Unable to open ucf!\n";
}
else
{
    die "Unknown format ".$ARGV[0]."\n";
}
shift @ARGV ;

(@ARGV) or die "No Part given!\n";

#split into blocks seperated with at least one empty line
@nets = split(/\n\n+/, $_);

Test if we got the right Thing
(@nets[0] eq "Netlist") or die "Probably no Eagle Netlist\n";

($keyword,$dummy) = split (/\s+/, @nets[2]);
($keyword eq "EAGLE") or die "Probably no Eagle Netlist\n";

#print comment
printf QCF "#" . @nets[1] . "\n";
printf QCF "#" . @nets[2] . "\n";
printf QCF "#Command line: " . $0;
for($argval = 0; $argval < @SAVEARGS; $argval++)
{
    printf QCF " \"" . $SAVEARGS[$argval] ."\"";
}
printf QCF "\n";

#print "Got ".@nets." Nets\n";
for ($nc =4; $nc < @nets;$nc++) # Eagle Netlist headers
{
    @connections = split(/\n/, $nets[$nc]); #dont strip newlines
    for ($cc = 0; $cc < @connections; $cc++) # scan through the line of a netlist)
    {
     ($dummy,$partname,$pad,$pin,$sheet)= split( /\s+/, $connections[$cc]);
     if (!$cc)
     {
         if ($dummy eq "Change") # a netlist generated from a schematics
         {
          $cc++;
          ($dummy,$partname,$pad,$pin,$sheet)= split( /\s+/, $connections[$cc]);
         }
         $netname = $dummy;
         if ($verbose)
         {
          print @connections . " Connections" . " for net: ". $netname . "\n";
         }
     }
#     print $connections[cc]."\n";
#     print "Net " . $netname . " Part " . $partname . " Pin " . $pin . " argv[0] ".$ARGV[0]."\n";
     if (($partname =~ m/\b$ARGV[0]\b/i) && !(($netname =~ m/\b$pad\b/) && ($no_stubs)))
     {
         for ($ac = 1; $ac <@ARGV; $ac++)
         {
          if ($verbose)
          {
              print "netname ".$netname." exclude ".$ARGV[$ac]."\n";
          }
          if ($netname =~ m/$ARGV[$ac]/i)
          {
              $ac = @ARGV +1;
          }
          if ($verbose)
          {
              print "netname ".$netname." ac ".$ac."\n";
          }
         }
         if ($verbose)
          {
              print "Net " . $netname . " Part " . $partname . " Pin " . $pin . " ac ".$ac." argc".@ARGV."\n";
          }
         if ($ac == @ARGV)
         {
          $_ = $netname;
          if ($verbose)
              {
               printf "Net %s Part %s Pad %s\n", $lowercase ? lc $_ : $_, $partname,$pad;
              }
          if ($useformat eq "QL")
          {
              s/$/sprintf("_p")/e;
              s/\d+_p/sprintf("_p[%d]",$&)/e;
              printf QCF "place %s IO%s\n",$lowercase ? lc $_ : $_, $pad;
          }
          elsif ($useformat eq "XIL")
          {
              s/\d+$/sprintf("<%d>",$&)/e;
                    if ($pad =~ m/^[a-z]/i)
                    {
                        printf QCF "NET \"%s\" LOC = \"%s\";\n",$lowercase ? lc $_:$_, $pad;
                    }
                    else
                    {
                        printf QCF "NET \"%s\" LOC = \"P%s\";\n",$lowercase ? lc $_:$_, $pad;
                    }
          }
         }
     }
    }
}
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel

Reply

autodeskguest over 11 years ago
gg <gendreau@optronis.com> wrote:
...
Example:
set_location_assignment PIN_A7 -to sensor_clk (from fpga pinout file)
This statement leads to the creation a wire named "sensor_clk" connected to
fpga pin A7.

Is it possible to do something like that?
I really didn't know how to start. I gave a look at "cmd-net-list2sch.ulp"
script but I can't make it work for a bga component.

So you let the FPGA tool choose the pins and you design the PCB after
routing the FPGA?

I do it the other way round. I design the board and give the choosen FPGA
pins as constraints to the FPGA placement. The constraint list is generated
form the eagle netlist with appended perl script. It is tested for
xilinx. Quicklogic is probably bit-rotten with time.

Bye
--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
-
Tel. 06151 162516 -
Fax. 06151 164321 -
#!/usr/bin/perl

Take a eagle board netlist and search for connections to a part. Exclude
selected nets,

Copyright Uwe Bonnes, 2002-2010 bon@elektron.ikp.physik.tu-darmstadt.de

net2ucf -h [excludepattern[s]]

This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Public License for more details.

if ((!@ARGV) ||($ARGV[0] eq "-h"))
{
    print "Usage: $0 -h ...\n";
    print "\t-h: print this help\n";
    print "\t-l: write netnames as lowercase\n";
    print "\t-v: verbose progress indication on stdout\n";
    print "\t-n: ignore stubs (Net named as pad)\n";
    print "\t[netlist]: a netlist exported from the Cadsoft Eagle Package\n";
    print "\t[format]= quicklogic|xilinx \n";
    print "\t[partdescriptor]: The name of the part to look for, e.g. \"IC1\"\n";
    print "\t[excludepattern] may be a regular expression\n";
    print "\te.g. $0 -i nets xilinx ic1 \"GND.\" \"VCC.\" \"JTAG_.*\"\n";
    print "\tOutput is written to {netlist].[pcf|ucf]\n";
    print "\tArguments are case sensitive\n";
    print "\tCheck resulting files!\n";
    exit 0;
}

@SAVEARGS= @ARGV;

while ($_ = $ARGV[0], /^-/)
{
    shift;
    last if /^--$/;
    if (/^-l(.*)/)
    {
     $lowercase = 1;
    }
    if (/^-v(.*)/)
    {
     $verbose = 1;
    }
    if (/^-n(.*)/)
    {
     $no_stubs = 1;
    }
}

if ($verbose)
{
    if ($lowercase)
    {
     print "Lowercase set\n";
    }
    else
    {
     print "Lowercase not set\n";
    }
    print "Verboseset\n";
}

if (!open (TXT, $ARGV[0] ))
{
    open (TXT, $ARGV[0] . ".net") or die "Unable to open $ARGV[0] and $ARGV[0].net!\n";
}

treat cr/lf:
$/ = "\r\n";
undef $/;
$_ = xilinx.ucf") or die "Unable to open ucf!\n";
}
else
{
    die "Unknown format ".$ARGV[0]."\n";
}
shift @ARGV ;

(@ARGV) or die "No Part given!\n";

#split into blocks seperated with at least one empty line
@nets = split(/\n\n+/, $_);

Test if we got the right Thing
(@nets[0] eq "Netlist") or die "Probably no Eagle Netlist\n";

($keyword,$dummy) = split (/\s+/, @nets[2]);
($keyword eq "EAGLE") or die "Probably no Eagle Netlist\n";

#print comment
printf QCF "#" . @nets[1] . "\n";
printf QCF "#" . @nets[2] . "\n";
printf QCF "#Command line: " . $0;
for($argval = 0; $argval < @SAVEARGS; $argval++)
{
    printf QCF " \"" . $SAVEARGS[$argval] ."\"";
}
printf QCF "\n";

#print "Got ".@nets." Nets\n";
for ($nc =4; $nc < @nets;$nc++) # Eagle Netlist headers
{
    @connections = split(/\n/, $nets[$nc]); #dont strip newlines
    for ($cc = 0; $cc < @connections; $cc++) # scan through the line of a netlist)
    {
     ($dummy,$partname,$pad,$pin,$sheet)= split( /\s+/, $connections[$cc]);
     if (!$cc)
     {
         if ($dummy eq "Change") # a netlist generated from a schematics
         {
          $cc++;
          ($dummy,$partname,$pad,$pin,$sheet)= split( /\s+/, $connections[$cc]);
         }
         $netname = $dummy;
         if ($verbose)
         {
          print @connections . " Connections" . " for net: ". $netname . "\n";
         }
     }
#     print $connections[cc]."\n";
#     print "Net " . $netname . " Part " . $partname . " Pin " . $pin . " argv[0] ".$ARGV[0]."\n";
     if (($partname =~ m/\b$ARGV[0]\b/i) && !(($netname =~ m/\b$pad\b/) && ($no_stubs)))
     {
         for ($ac = 1; $ac <@ARGV; $ac++)
         {
          if ($verbose)
          {
              print "netname ".$netname." exclude ".$ARGV[$ac]."\n";
          }
          if ($netname =~ m/$ARGV[$ac]/i)
          {
              $ac = @ARGV +1;
          }
          if ($verbose)
          {
              print "netname ".$netname." ac ".$ac."\n";
          }
         }
         if ($verbose)
          {
              print "Net " . $netname . " Part " . $partname . " Pin " . $pin . " ac ".$ac." argc".@ARGV."\n";
          }
         if ($ac == @ARGV)
         {
          $_ = $netname;
          if ($verbose)
              {
               printf "Net %s Part %s Pad %s\n", $lowercase ? lc $_ : $_, $partname,$pad;
              }
          if ($useformat eq "QL")
          {
              s/$/sprintf("_p")/e;
              s/\d+_p/sprintf("_p[%d]",$&)/e;
              printf QCF "place %s IO%s\n",$lowercase ? lc $_ : $_, $pad;
          }
          elsif ($useformat eq "XIL")
          {
              s/\d+$/sprintf("<%d>",$&)/e;
                    if ($pad =~ m/^[a-z]/i)
                    {
                        printf QCF "NET \"%s\" LOC = \"%s\";\n",$lowercase ? lc $_:$_, $pad;
                    }
                    else
                    {
                        printf QCF "NET \"%s\" LOC = \"P%s\";\n",$lowercase ? lc $_:$_, $pad;
                    }
          }
         }
     }
    }
}
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel

Children

No Data