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EAGLE User Support (English) Generate schematic automatically from FPGA pi nout?
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Related

Generate schematic automatically from FPGA pi nout?

autodeskguest
autodeskguest over 11 years ago

Hi,

 

I used to create FPGA schematic manually but my last project has a 1500pins

FPGA and I would like to automate things to avoid errors and also save some

time.

I am a beginner in ULP scripts so I would appreciate some advice.

 

I didn't find any way to automate passing from FPGA pinout in (Quartus .qsf

file for example) to board schematic.

I have this procedure in mind:

- create FPGA symbol/package with "make-symbol-device-package-bsdl.ulp"

(already done)

- add a FPGA part on a schematic sheet

Then an ulp script has to:

- Parse Altera pinout file (qsf) to extract signal and pin names

- For each fpga symbol pin mentioned in the FPGA pinout file:

=> Trace and connect a wire to the fpga symbol pin

=> Label this wire with the signal name from .qsf file and display the

name

 

Example:

set_location_assignment PIN_A7 -to sensor_clk (from fpga pinout file)

This statement leads to the creation a wire named "sensor_clk" connected to

fpga pin A7.

 

Is it possible to do something like that?

I really didn't know how to start. I gave a look at "cmd-net-list2sch.ulp"

script but I can't make it work for a bga component.

 

Thanks in advance for helping.

 

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

 

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  • autodeskguest
    autodeskguest over 11 years ago

    Thanks for replies.

     

    @Chuck:

    Your method seems to be interesting, I will gave a look at scripts

    capabilities.

     

    @Uwe Bonnes:

    I use a lot a high speed IOs (lvds, ddr3, sata III...) with several

    different voltages. These kind of IO have many placement restrictions and

    they also impact nearby pins availability so you must validate pinout with

    the FPGA software.

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

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  • autodeskguest
    autodeskguest over 11 years ago

    Thanks for replies.

     

    @Chuck:

    Your method seems to be interesting, I will gave a look at scripts

    capabilities.

     

    @Uwe Bonnes:

    I use a lot a high speed IOs (lvds, ddr3, sata III...) with several

    different voltages. These kind of IO have many placement restrictions and

    they also impact nearby pins availability so you must validate pinout with

    the FPGA software.

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

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