Generate schematic automatically from FPGA pi nout?

On 20/01/2014 11:25 p.m., gg wrote:

Hi,

 

I used to create FPGA schematic manually but my last project has a 1500pins

FPGA and I would like to automate things to avoid errors and also save some

time.

I am a beginner in ULP scripts so I would appreciate some advice.

 

I didn't find any way to automate passing from FPGA pinout in (Quartus .qsf

file for example) to board schematic.

I have this procedure in mind:

- create FPGA symbol/package with "make-symbol-device-package-bsdl.ulp"

(already done)

- add a FPGA part on a schematic sheet

Then an ulp script has to:

- Parse Altera pinout file (qsf) to extract signal and pin names

- For each fpga symbol pin mentioned in the FPGA pinout file:

=> Trace and connect a wire to the fpga symbol pin

=> Label this wire with the signal name from .qsf file and display the

name

 

Example:

set_location_assignment PIN_A7 -to sensor_clk (from fpga pinout file)

This statement leads to the creation a wire named "sensor_clk" connected to

fpga pin A7.

 

Is it possible to do something like that?

I really didn't know how to start. I gave a look at "cmd-net-list2sch.ulp"

script but I can't make it work for a bga component.

 

Thanks in advance for helping.

 

.

Totally do-able with a ULP. I imagine the process would be something

like this:

run MyULP.ulp

Dialog opens and you enter the FPGA name from the schematic (say U1)

In that same dialog you select the .qsf file of interest.

ULP parses the  file and matches pin names to qsf data

Identifies pin location,direction, and creates a script that runs when

the ULP ends

It draws a short named net wire out from the pin in the appropriate

direction and labels it with the signal name.

This is exactly as you imagined.

Quartus has other export file types that may be easier to parse than .qsf

Down side of the idea is schematic symbols stay presented by pin number

and not signal grouping but you need only have one library part for the

device type.

HTH

Warren

On 20/01/2014 11:25 p.m., gg wrote:

Hi,

 

I used to create FPGA schematic manually but my last project has a 1500pins

FPGA and I would like to automate things to avoid errors and also save some

time.

I am a beginner in ULP scripts so I would appreciate some advice.

 

I didn't find any way to automate passing from FPGA pinout in (Quartus .qsf

file for example) to board schematic.

I have this procedure in mind:

- create FPGA symbol/package with "make-symbol-device-package-bsdl.ulp"

(already done)

- add a FPGA part on a schematic sheet

Then an ulp script has to:

- Parse Altera pinout file (qsf) to extract signal and pin names

- For each fpga symbol pin mentioned in the FPGA pinout file:

=> Trace and connect a wire to the fpga symbol pin

=> Label this wire with the signal name from .qsf file and display the

name

 

Example:

set_location_assignment PIN_A7 -to sensor_clk (from fpga pinout file)

This statement leads to the creation a wire named "sensor_clk" connected to

fpga pin A7.

 

Is it possible to do something like that?

I really didn't know how to start. I gave a look at "cmd-net-list2sch.ulp"

script but I can't make it work for a bga component.

 

Thanks in advance for helping.

 

.

Totally do-able with a ULP. I imagine the process would be something

like this:

run MyULP.ulp

Dialog opens and you enter the FPGA name from the schematic (say U1)

In that same dialog you select the .qsf file of interest.

ULP parses the  file and matches pin names to qsf data

Identifies pin location,direction, and creates a script that runs when

the ULP ends

It draws a short named net wire out from the pin in the appropriate

direction and labels it with the signal name.

This is exactly as you imagined.

Quartus has other export file types that may be easier to parse than .qsf

Down side of the idea is schematic symbols stay presented by pin number

and not signal grouping but you need only have one library part for the

device type.

HTH

Warren

Yes you are right. After reading some ulp examples and ulp doc this was not

so complicated.

The script 'cmd-net-list2sch.ulp' helps a lot to understand how to access:

- Pin.name

- Pin.coord(x, y)

- trace and label wires with 'NET' and 'LABEL' commands

To parse quartus qsf file I just search for string "set_location_assignment

PIN_". Then its easy to get pin and signal names.

Finally loop on fpga schematic pins and compare Pin.name to the name

extracted from .qsf and trace a wire if name are the same.

--

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