Error messages during simulation with Eagle-PCBsim: timestep too small, iteration limit exceeded: what next?

Question

Using PCBsim in a circuit intended to produce fast changing voltages I often get errors: " timestep too small" or " iteration limit exceeded".

In one case this was cured by pulling up/down a certain net in the circuit to GND via 10k resistors.

However, pulling these nets to the rail voltages +/- 24 V via the same resistor again led to the errors.

This looks confusing to me.

How can one deal with such internal(?) PCBsim errors?

Thanks,

Jan

autodeskguest · Accepted Answer

Hi Jan, Here's is Heinz's response. " Hi Jorge, This is a very general error meaning the circuit does not converge. There are a number of possible root causes ("non-physical" circuits, extremely small and large currents / voltages in one circuit, bad mannered simulation models, ...). To rectify, the following steps can be tried: a) Change the convergence settings to "moderate" or "forgiving". b) Make the timestep smaller (simulation settings, transient analysis). c) Add small stray capacitances (for example 0.1pF) to critical nets. d) Change the output resistance of voltage sources (make it for example 1mOhm or 1Ohm) e) Add parasitic resistance parallel to inductances (for example 1GOhm). Each of this proposals has a whole story behind it. I'm adding just a few (hopefully helpful) remarks: c) Adding small capacitances to critical nets: The Spice algorithm automatically adjusts time step sizes. If a circuit changes rapidly, the time step is made smaller. Only when ALL circuit voltages and monitored currents are accurate below the convergence thresholds (see a), the time step is accepted. Small capacitances help to make a circuit well-behaved with small time steps, that is that voltages and currents do not change strongly for very short time steps. The added capacitors should be of a size which does NOT change the desired circuit behaviour. Often it is enough to add stray capacitance which are present in a real circuit anyway. d) Changing the output resistance of voltage sources Very "stiff" elements are problematic for the convergence algorithm. Stiff means that changing one parameter (for example output current) does not have an effect on another parameter (output voltage). Therefore, pure voltage sources with zero output resistances are often difficult to converge. Unfortunately some simulation models for operational amplifiers behave very critical to voltage sources with an impedance. The model might cause non-physical currents flowing into or out of the supply voltage. Then, the source impedance needs to be made very small (1µOhm). e) Parallel resistance to inductors This again makes sure that a the device behaves less stiff. With very small time steps, a voltage change across the inductor will otherwise not lead to a current change. If you still do not succeed, you can send your circuit together with any special simulation models to support@felicitas-ce.de . Your design will of course be treated confidentially. With best regards, Heinz "