How do I create mounting hole with vias

On 02.06.2016 19:22, Marek Kepinski wrote:

I'm looking for a way to create mounting hole with 6 vias (as a library component) for M3 screw. I was able to create such a package but when I use it on a board and run DRC, I get "Overlap" errors. The vias are defined as small pads since vias are not available in library designer. Is there a way to get rid of the errors? I remember that I was able to define such a component in KiCAD and I' surprised that in Eagle it is that difficult.

Here: pcb design - Mounting hole on a PCB - Electrical Engineering Stack Exchange (http://electronics.stackexchange.com/questions/137394/mounting-hole-on-a-pcb)  is an example of such a mounting hole (the right most on the photo).

First, at the rightmost picture on the link you send, the vias are not

needed, as the hole is already plated, but I think it can be done with a

large pad + smaller pads overlapping all in the package. And all those

pads need to be appended to a single symbol pin.

If you prefer the non plated (middle pic), your package needs vias

surrounded with a polygon, all appended to one pin, and the masks

manually made ofcourse.

On 02.06.2016 19:22, Marek Kepinski wrote:

I'm looking for a way to create mounting hole with 6 vias (as a library component) for M3 screw. I was able to create such a package but when I use it on a board and run DRC, I get "Overlap" errors. The vias are defined as small pads since vias are not available in library designer. Is there a way to get rid of the errors? I remember that I was able to define such a component in KiCAD and I' surprised that in Eagle it is that difficult.

Here: pcb design - Mounting hole on a PCB - Electrical Engineering Stack Exchange (http://electronics.stackexchange.com/questions/137394/mounting-hole-on-a-pcb)  is an example of such a mounting hole (the right most on the photo).

First, at the rightmost picture on the link you send, the vias are not

needed, as the hole is already plated, but I think it can be done with a

large pad + smaller pads overlapping all in the package. And all those

pads need to be appended to a single symbol pin.

If you prefer the non plated (middle pic), your package needs vias

surrounded with a polygon, all appended to one pin, and the masks

manually made ofcourse.

Thanks for the answer but I need a little bit more information on the "append" action. I tried it but the "Overlap" error didn't disappear. I also get some other strange problems: I add the package to the board (it is connected to GND on the schematic). I surround the package with a polygon, rename it to GND and fill with ratsnest. At this moment the two small pads ("vias") are connected with a track, the polygon disappears. My target is to get rid of the "Overlap" error and to be able to connect it to GND, or leave it unconnected (with filled polygons around the package). Any ideas?

Mark

I have some progress. The problems that I had with polygon were a result of the way I tested the package. There were no other tracks on the board and no other components inside the polygon. After correcting this the solution almost works. It looks like this:

The "Overlap" error is not reported now. But the pad is not connected to the ground despite the fact that the polygon is "GND" , the mounting holes are connected to GND on the schematic and the package has "Thermals" option checked. How can I correct this problem?

Also two vias are connected with track but this will be removed during drilling of the board. Why this track is displayed?

The current solution uses "append" feature (as suggested), the pads are marked as disconnected (with little green icon) and "@x" in the names of the small pads (but I'm not sure whether this is important).

Mark

On 04/06/16 07:50, markusbass wrote:

I have some progress. The problems that I had with polygon were a result of the way I tested the package. There were no other tracks on the board and no other components inside the polygon. After correcting this the solution almost works. It looks like this:

The "Overlap" error is not reported now. But the pad is not connected to the ground despite the fact that the polygon is "GND" , the mounting holes are connected to GND on the schematic and the package has "Thermals" option checked. How can I correct this problem?

Also two vias are connected with track but this will be removed during drilling of the board. Why this track is displayed?

The current solution uses "append" feature (as suggested) and "@x" in the names of the small pads (but I'm not sure whether this is important).

 

The presence of those stray tracks suggests the hole isn't really a hole

(or isn't present on all the layers a hole should be on) since tracks

that pass through holes should throw DRC errors. Can they be ripped up?

The airwires remaining after a ratsnest suggests that your pads are not

connected to the same net as the polygon. This could be because they're

unconnected - if your library symbol names them GND that is not enough

to make them GND pins. Either the schematic must connect them to GND or

the pins on the library part must be "power" pins called GND (and

possibly hidden on an uninvoked symbol, not sure on that).

Personally, I'd name the pins/pads in the library as something generic,

then explicitly connect to GND on the schematic. It makes for more

clarity and flexibility.

On 4/06/2016 6:50 p.m., markusbass wrote:

I have some progress. The problems that I had with polygon were a result of the way I tested the package. There were no other tracks on the board and no other components inside the polygon. After correcting this the solution almost works. It looks like this:

The "Overlap" error is not reported now. But the pad is not connected to the ground despite the fact that the polygon is "GND" , the mounting holes are connected to GND on the schematic and the package has "Thermals" option checked. How can I correct this problem?

Also two vias are connected with track but this will be removed during drilling of the board. Why this track is displayed?

The current solution uses "append" feature (as suggested) and "@x" in the names of the small pads (but I'm not sure whether this is important).

 

Mark

 

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To view any images and attachments in this post, visit:

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The track between two vias is likely to be a polygon orphan.

Review the attached library.

It gives a PTH mounting hole and 6 stitching vias.

When you set DRC to appropriate values there are no DRC errors.

Ignore the sizes in this example and create sizes that suit you.

If you don't get the attachment at E14. Get it from the news,cadsoft.de

newsgroup or the EagleCentral.ca mirror.

HTH

Warren

Thank you - this is almost what I was looking for. Regarding previous remarks to my screenshot: you were right, there were problems with the pad. I created the package as a copy of another package and it looks like I shouldn't do it. I started the package from scratch and got much better results. Actually, the same as Warren presented.

On the left there are two pads from my library, one connected to the ground and the other not. On the right are two pads from Warren's library. There are just small differences. I have the drill = 3.2mm and Warren has 3.5mm. Warren's pad didn't have the "Thermals" option checked - I had to change it. The problem is with pads not connected to the ground. As you can see, in both cases "vias" as reported as "Overlap" by DRC. How can I get rid of this last error?

Mark

  As you can see, in both cases "vias" as reported as "Overlap" by DRC.

How can I get rid of this last error?

I believe your issue is :

The mounting hole giving the overlap errors has a schematic symbol with

a pin that is not connected to any net. Perform an ERC and you will see

the unconnected pin listed.

Simply apply a stub net to that pin and the overlap errors go away.

HTH

Warren

  As you can see, in both cases "vias" as reported as "Overlap" by DRC.

How can I get rid of this last error?

I believe your issue is :

The mounting hole giving the overlap errors has a schematic symbol with

a pin that is not connected to any net. Perform an ERC and you will see

the unconnected pin listed.

Simply apply a stub net to that pin and the overlap errors go away.

HTH

Warren

Thank you very much. yes, this was the problem. Adding a stub net to that pin solved the problem. I'd like to mark this answer as "Correct Answer" but the answer is spread between various posts.

I have just last question:

It seems that there are still some differences between my a Warren's library. When I move the grounded pads away, one can see that the thermal tracks generated with my library are different width, while tracks from Warren's library are perfect.

What can cause this difference?

Mark