Re: Routing overlap problems

"David Pollum" <vze24h5m@verizon.net> wrote in message

news:fm5iba$4pp$1@cheetah.cadsoft.de...

Ron wrote:

 

"Richard Hammerl" <ric@cadsoft.de> wrote in message

news:flsu6v$s66$1@cheetah.cadsoft.de...

<snip>

 

there seem to be lots of trouble with your board. Could you meanwhile

solve all the problems? If no, please send me the board file with

private mail so that I can check it.

 

 

--

Mit freundlichen Gruessen / Best regards

Richard Hammerl

CadSoft Support -- hotline@cadsoft.de

FAQ: http://www.cadsoft.de/faq.htm

 

Offer much appreciated, but the "problem" is the newbie (me!) learning

curve. For example, it didn't really sink in until I came across a

message that I don't have to add a polygon in the Dimension layer, a line

will do along with proper Drc "Distance" settings. And the layer being

drawn on during routing, well, that too gets set in the "Route" section

of Drc. Via's occuring on power traces, well, I suspect it was just my

view of that board that used burried via's, turning off display layers I

don't think turns off seeing all burried via's on a turned off layer if

the display is set to show just 1 layer and via's; most houses seem to

give better deals if only via's that go through all layers are used

anyway. The Class thing works fine, but it was by pure curiosity that I

discovered that once I set Change|Class all I had to do was click a net

either in the schematic or the board editor and from thereon it would be

'remembered' in the project (needed for various size net widths). Now, I

don't think I really had 'overlaps' but instead was seeing all via's when

viewing just 1 layer, instead of just the via's that the layer has!

 

Ok, I know I sound stupid. I am! This is a difficult program to learn how

to use and too much documentation doesn't point back to things that one

really needs to already understand in order to then understand what is

being researched. But don't get me wrong, it's just a learning curve and

I am very impressed with how well Eagle works with or without quirks!

It's just that my 1st project, out of necessity and time constraints, had

to be a 4x5" board, 4 layers, with 31 IC's on it... it was "learn by

doing" because of that constraint on my time. But, I've done it, and I

understand a LOT more than I did just 2 weeks ago, and the gerber files

have even passed online testing.<grin>

 

I will, however, send ya copy of the project soon. I decreased the board

editor grid settings (have good reasons) and did some other improvements,

and so of course now it takes much longer (near 24 hours vs 6) to

autoroute but traces are closer (grid is finer, allowing Drc settings to

be effective). It's cooking at home now, on a darn fast computer, as I

write this just before I start work at my 'day job'...

-Ron

Ron;

 

That sounds like a pretty complicated board for a newbie to layout.  Are

you just a newbie with EAGLE, or are you a PCB layout newbie, too?  I'd be

interested in seeing the latest version of the board.

-Dave Pollum

My apology for the long response time.

Well, Dave and Richard, the answer is yes & yes. But decades away from being

a newbie to electronics itself. The breadboarded project circuit, and

software to use it, works. Regrettably, getting into board design is

something I should have gotten into at least a decade ago, as I find the

learning curve much steeper than anticipated. But ok, if I've made so much

noise that now 2 people have requested to see the board then I am grateful

and I'd like to comply. But I can not disclose the schematic. How do I go

about this, just send the 157k .brd file? Is it necessary to include any non

standard library I've created for the board, or anything else beyond just

the .brd file? Is it allowed to attach it to a reply to this ng topic even

though its 157k?

I'm still fighting 2 remaining battles.

freeDFM is complaining that all my vias have an annular ring (restring)

of 0mil, but my DRC table for vias looks identical to page 102 in the manual

(8mil/25%/20mil) and I changed the default class to read 6mil/6mil/15mil, so

I think at a drill of 15mil the ring is 16mil and not 0mil.

freeDFM is complaining that all text associated with all (yes, all)

packages is too small. I've no idea how to fix that without editing the

respective libraries, since smashing isn't the answer.

-Ron

I'm still fighting 2 remaining battles.

freeDFM is complaining that all my vias have an annular ring (restring)

of 0mil, but my DRC table for vias looks identical to page 102 in the manual

(8mil/25%/20mil) and I changed the default class to read 6mil/6mil/15mil, so

I think at a drill of 15mil the ring is 16mil and not 0mil.

I have see freeDFM get confused when you have a polygon over a via/pad.

freeDFM is complaining that all text associated with all (yes, all)

packages is too small. I've no idea how to fix that without editing the

respective libraries, since smashing isn't the answer.

-Ron

There are ULP's which fix it but that is one reason to have "your lib"

in which you copy all of the parts you need and fix them to your

requirements. After smashing you can group all of the text and change

the ratio. You may find that some of the silkscreen lines are too thin also.

Paul R.

Ron wrote:

I'm still fighting 2 remaining battles.

freeDFM is complaining that all my vias have an annular ring (restring)

of 0mil, but my DRC table for vias looks identical to page 102 in the manual

(8mil/25%/20mil) and I changed the default class to read 6mil/6mil/15mil, so

I think at a drill of 15mil the ring is 16mil and not 0mil.

freeDFM is complaining that all text associated with all (yes, all)

packages is too small. I've no idea how to fix that without editing the

respective libraries, since smashing isn't the answer.

-Ron

 

 

As for the FreeDMF text size, either allow 4PCB to do their auto fixes, or:

Turn off all layers except part tOrigins and bOrigins and Select all

parts with group select and smash them all.

Then turn off all layers except tNames and bNames and select all with

group select.

Then go to Change Ratio...

Set a larger ratio and right click on the group.

Personally I wish we could just set a minimum line width for text; it

would be so much easier.

--

Travis Grenell

The CarPC Store

404-403-0556

http://www.TheCarPCStore.com

"Paul Romanyszyn" <pgr@arcelectronicsinc.com> wrote in message

news:focl6b$5bf$1@cheetah.cadsoft.de...

I have see freeDFM get confused when you have a polygon over a via/pad.

Thanks for the reply, Paul! That's regarding freeDFM saying all my vias of

any size have an annular ring (restring) size of zero. I've not drawn any

polygons at all.

When I look at the freeDFM pictures it looks like all I have is via pads

with no drill holes, it all looks filled in. But in the board editor all

looks as it should. I did send an Excelon file to them. For one of the

pictured problem vias, the editor Info command gives me a report saying its

diameter is "0.031/0.031 (auto)" in inches, and I don't understand why it's

giving 2 parameters in those quotes but I do see that one divided by the

other does = zero and I wonder if that's the problem? For that via, the

drill is set at .015".

I've made the .brd file (only that file) available for anyone to see at:

http://www.RGMEusa.com/Misc/USBto64RW.zip

It doesn't include the silkscreen fixes, which I did on a different computer

last night. I only have the restring problem remaining. I don't think I can

fix it without doing a rip, so I'm not ripping until I understand the cause

of the vias problem with freeDFM.

-Ron

"Travis G" <fightspammers@gmail.com> wrote in message

news:focpoo$e9k$1@cheetah.cadsoft.de...

As for the FreeDMF text size, either allow 4PCB to do their auto fixes,

or:

Turn off all layers except part tOrigins and bOrigins and Select all parts

with group select and smash them all.

Then turn off all layers except tNames and bNames and select all with

group select.

Then go to Change Ratio...

Set a larger ratio and right click on the group.

 

Personally I wish we could just set a minimum line width for text; it

would be so much easier.

Travis, that worked very well - thanks much for the tip. Did it last night

and assured I had ratio of 10 and at least 0.06" size text in all of the

silkscreen. After I get the via problem resolved (probably going to require

a rip, though) then I'll be able to see if freeDFM is happy or not. Again,

thanks for the procedural tip - I didn't  realize I could smash a group

selected on an origins layer, that's a real time saver! I still had to edit

one library package (the 1st one I ever made, I had drawn >NAME on the wrong

layer so I couldn't smash it), and I'll use the replace command to re-insert

the edited part onto the board again. 

-Ron

I've split to a new topic regarding the issue I have with vias & freeDFM, as

it is off topic to this thread (which should be closed anyhow) and that

makes it hard for others in the future to find the pertinent conversation.

The new topic name is:  freeDFM & via issue

My thanks again to all who have submitted comments in this here thread.

-Ron