freeDFM & via issue

Ron wrote:

Others said similar and John Giddy wrote:

Ron,

Even low speed logic circuitry can generate transient oscillations due to

the fast rise time of common digital ICs. This fast rise time causes the

power supply to "see" sharp changes in demand for power, giving quite

large voltage transients due to circuit inductance. This can propagate to

adjacent circuits. The bypass capacitor provides this transient power to

prevent or at least greatly reduce the spike on the supply line. I think

you are being too optimistic that all will be well, just because the

prototype worked OK.

If this is a production board, with many to be made, tolerances could well

give you a reasonable proportion which cause problems. It is easier, and

not very expensive to add bypass capacitors at the start.

John G.

 

I agree with everyone that bypass caps are good design practice and, as you

say John, easier and cheaper to add at the start of a project than to have

to implement the practice after a production run. As was also pointed out,

power planes are also good design practice. I wish I could divulge the

schematic so that my arguments about both being unnecessary in this

particular design could more easily be examined, but I'm not at liberty to

divulge it.

 

The  UM245RUM245R USB module has 7 I/O pins programmed as latching outputs one pin

as an input, and operates in self powered mode. It is only at the USB cable

connection, part of the chip module itself, are there any repetitive signals

that even approach a frequency that might cause unwanted parasitic

oscillations of any resonance. Everywhere else on the board the signals are

latched.

 

Logic level changes that, for whatever reason, would tend to start an

oscillation quickly get swamped by the fact that the circuits are latched

and continually refreshed (at a chips settling time rate, very fast) as a

state machine rather than being sampled in reoccurring clocked time states.

State machines, unlike clocked machines, inherently suppress oscillations

and that's an important design fact. Just because signal patterns do change

doesn't mean all patterns are going to induce transient oscillations

(resonance) and that's because only one bit pattern state might have such a

tendency in a particular board location. In this design any one physical

location only has 1 chance in 128 of instigating a parasitic oscillation

but, even if the tendency exists, the bit pattern isn't changing (it is

latched) and so the resonance tank does not get pumped and so the tendency

to oscillate is greatly attenuated to the point where oscillation is super

unlikely. MUCH more so than in clocked circuits.

 

Even if an oscillation started it will not affect the latched source

signals and those latched signals from the  UM245RUM245R will quickly suppress any

tendency to oscillate. This is the advantage of a state machine over a

clocked machine; by their very nature oscillations are suppressed (thus

greatly decreasing needs for bypass caps). Since only a changing output

pattern from the  UM245RUM245R might tend to instigate an oscillation it is still

a latched output that fights that tendency, it does not rely on "data valid"

clocking that would have a MUCH higher tendency to oscillate (the clock

itself getting spurious signals Yes I use one  UM245RUM245R output pin to

establish a read or write condition to the rest of the circuitry, but it too

is latched and not clocked. It wouldn't hurt to add the bypass caps, but in

this design they would be redundant and an unnecessary expense because the

bottom line is that latching suppresses oscillations.

 

Not having power planes isn't really what I wanted. The bigger the power

trace then the less voltage drop will appear across it, and anywhere there

is a voltage drop there is also a potential avenue into oscillations. But I

have too many connection points, I would need to have more than 4 layers if

I use power planes. So I compromised by using huge power traces and keeping

them all to the bottom layer (I route them first). 6mil distance for power

traces is bad, I need to pick a distance value that is not a harmonic length

of chip settling time, even in a latching circuit. I forgot to do that when

I created the class in Eagle but it will be in the final routing.

 

I have chosen not to implement the additional safety of adding bypass caps

because in a 100% latching based circuit the need is redundant, it would

require around 100 more drills and the project surely would then be

unroutable in just 4 layers. The same reasoning went into my decision not to

use power planes in this particular design, I simply could not route for 4

layers at the needed board size even if I included just a ground plane only.

Too many connection points. I don't like the compromises at all, but the

effect of those 2 decisions in this particular case is so near to being a

zero impact as to be considered very tolerable.

-Ron

 

 

Good luck...

John G.

Ron wrote:

Others said similar and John Giddy wrote:

Ron,

Even low speed logic circuitry can generate transient oscillations due to

the fast rise time of common digital ICs. This fast rise time causes the

power supply to "see" sharp changes in demand for power, giving quite

large voltage transients due to circuit inductance. This can propagate to

adjacent circuits. The bypass capacitor provides this transient power to

prevent or at least greatly reduce the spike on the supply line. I think

you are being too optimistic that all will be well, just because the

prototype worked OK.

If this is a production board, with many to be made, tolerances could well

give you a reasonable proportion which cause problems. It is easier, and

not very expensive to add bypass capacitors at the start.

John G.

 

I agree with everyone that bypass caps are good design practice and, as you

say John, easier and cheaper to add at the start of a project than to have

to implement the practice after a production run. As was also pointed out,

power planes are also good design practice. I wish I could divulge the

schematic so that my arguments about both being unnecessary in this

particular design could more easily be examined, but I'm not at liberty to

divulge it.

 

The  UM245RUM245R USB module has 7 I/O pins programmed as latching outputs one pin

as an input, and operates in self powered mode. It is only at the USB cable

connection, part of the chip module itself, are there any repetitive signals

that even approach a frequency that might cause unwanted parasitic

oscillations of any resonance. Everywhere else on the board the signals are

latched.

 

Logic level changes that, for whatever reason, would tend to start an

oscillation quickly get swamped by the fact that the circuits are latched

and continually refreshed (at a chips settling time rate, very fast) as a

state machine rather than being sampled in reoccurring clocked time states.

State machines, unlike clocked machines, inherently suppress oscillations

and that's an important design fact. Just because signal patterns do change

doesn't mean all patterns are going to induce transient oscillations

(resonance) and that's because only one bit pattern state might have such a

tendency in a particular board location. In this design any one physical

location only has 1 chance in 128 of instigating a parasitic oscillation

but, even if the tendency exists, the bit pattern isn't changing (it is

latched) and so the resonance tank does not get pumped and so the tendency

to oscillate is greatly attenuated to the point where oscillation is super

unlikely. MUCH more so than in clocked circuits.

 

Even if an oscillation started it will not affect the latched source

signals and those latched signals from the  UM245RUM245R will quickly suppress any

tendency to oscillate. This is the advantage of a state machine over a

clocked machine; by their very nature oscillations are suppressed (thus

greatly decreasing needs for bypass caps). Since only a changing output

pattern from the  UM245RUM245R might tend to instigate an oscillation it is still

a latched output that fights that tendency, it does not rely on "data valid"

clocking that would have a MUCH higher tendency to oscillate (the clock

itself getting spurious signals Yes I use one  UM245RUM245R output pin to

establish a read or write condition to the rest of the circuitry, but it too

is latched and not clocked. It wouldn't hurt to add the bypass caps, but in

this design they would be redundant and an unnecessary expense because the

bottom line is that latching suppresses oscillations.

 

Not having power planes isn't really what I wanted. The bigger the power

trace then the less voltage drop will appear across it, and anywhere there

is a voltage drop there is also a potential avenue into oscillations. But I

have too many connection points, I would need to have more than 4 layers if

I use power planes. So I compromised by using huge power traces and keeping

them all to the bottom layer (I route them first). 6mil distance for power

traces is bad, I need to pick a distance value that is not a harmonic length

of chip settling time, even in a latching circuit. I forgot to do that when

I created the class in Eagle but it will be in the final routing.

 

I have chosen not to implement the additional safety of adding bypass caps

because in a 100% latching based circuit the need is redundant, it would

require around 100 more drills and the project surely would then be

unroutable in just 4 layers. The same reasoning went into my decision not to

use power planes in this particular design, I simply could not route for 4

layers at the needed board size even if I included just a ground plane only.

Too many connection points. I don't like the compromises at all, but the

effect of those 2 decisions in this particular case is so near to being a

zero impact as to be considered very tolerable.

-Ron

 

 

Good luck...

John G.