freeDFM & via issue

Ron wrote:

"Guy" <guy.dau_no_spam@free.fr> wrote in message

news:foiedu$vrq$1@cheetah.cadsoft.de...

"Ron" <Use@Forum.pls> a écrit dans le message de news:

foicn5$rug$1@cheetah.cadsoft.de...

"Guy" <guy.dau_no_spam@free.fr> wrote in message

news:fohqh1$sgn$1@cheetah.cadsoft.de...

Hi,

 

When I'm testing it I have just one DRC error with design rule

www.my4pcb.com you have select !!!

 

Guy

 

PS: I'm affray, you don't use any condensators on this card !!!

I think you must minimum add decouplers condensators to be sure work ok

!!!

Yes, that version had too tight of clearance for those 2 pins - I

corrected that already. Annoyed me, as when I auto routed that one trace

the DRC rules were not followed and I had to move the trace manually one

grid away from IC1. Luckily, there is a DRC check button!<smile>

 

Guy, this design (and the hand wired proto) definitely does not need VCC

bypass capacitors. It's a state machine, no clocking, and the USB module

(it's not a chip) includes its own decoupling to the USB buss; what that

module connects to is not powered by the USB buss and it is rather slow

and usually just sitting in one state. I do, however, need to (or should)

increase distance between the Power class traces. I gotta rip again

anyhow when I find out why freeDRM doesn't like the vias, I'll change the

class then.

-Ron

No !!

 

It's not because it's a state machine and no clocking then decoupling is

not necessary !!!

 

With all these circuits and not decoupling, alimentation can start in

resonance !!!

 

With many TTL and CMOS you don't know alimentation reaction !!

 

I think you must define any bypass/de-coupling and after perhaps not

necessary to put all but you don't know !!!!!

 

After many years of electronic developpement.......

 

Sorry for my english,

 

Guy

 

This is getting way off topic but I do respect and appreciate your usage of

English, please do not apologize. Although you could use a few less "!!!!!"

characters!!!!! <vbg> You are understandable and if the situation were

reversed I'd be, knowing only English, unable to return the courtesy.  But

most of all I respect your knowledge.

 

I would again try to qualify my agreement with what you say, which I believe

to be a reference to a phenomenon known as parasitic resonance and which is

a common annoyance in RF circuits. RF infers oscillation, and oscillating

circuits have maximum power response at a resonant frequency.  My point is

that there must be oscillation before there can be resonance, parasitic or

not. This occurs in digital circuits primarily because of repeating patterns

of current flow at high bit level changing rates (what I mean by "clocked",

be it data pattern repetition or any other time base). The capacitive

"decoupling" or "bypassing" is actually the detuning of the resonant

circuit, dampening the amplitude of unintended oscillations to negligible

level.  This is usually a very important consideration.

 

But, if my design works (and the prototype does) and it experiences

oscillations then it is malfunctioning because the amplitude of the

oscillation would have to be of sufficient energy as to overpower the power

supply as relates to the guaranteed high or low level specified for a gate

input. If the power supply is working and distributed properly then that

would have to be a rather huge amount of energy.  Without oscillation there

can be no resonance.  If there can be no resonance then decoupling is not

required.

 

In this board all I/O is inherently latched. Even when changing at USB 2.0

speed, the amount of time between cycles of a particular bit pattern that

just happens to be resonant is what keeps enough energy from entering the

tank to build sufficiently to overcome the power supply to a level where a

gate would see a logic change. There simply aren't enough such cycles within

a sufficiently small enough time period to build enough energy in a tank to

sustain oscillation. If Murphy gets into the act regardless, then the

mentioned time period can be lengthened by slowing down USB usage - thus

detuning the tank.

 

This board is an exception to the general rule that decoupling should be

used. Primarily because it is latched and not clocked by some means.

Repetitive tank pumping is not likely because repetitiveness does not exist

in a latched circuit like it does in a clocked circuit. It would not hurt to

use decoupling, except for production cost. My only worry with the entire

design is that I might be exceeding the fan out rating of the USB module. If

so, the resultant instability is not due to resonance or oscillation. On

this board decoupling would be of little use, malfunction must begin before

resonant oscillation can occur.

-Ron

 

 

Ron,

Even low speed logic circuitry can generate transient oscillations due

to the fast rise time of common digital ICs. This fast rise time causes

the power supply to "see" sharp changes in demand for power, giving

quite large voltage transients due to circuit inductance. This can

propagate to adjacent circuits. The bypass capacitor provides this

transient power to prevent or at least greatly reduce the spike on the

supply line. I think you are being too optimistic that all will be well,

just because the prototype worked OK.

If this is a production board, with many to be made, tolerances could

well give you a reasonable proportion which cause problems. It is

easier, and not very expensive to add bypass capacitors at the start.

John G.

Ron wrote:

"Guy" <guy.dau_no_spam@free.fr> wrote in message

news:foiedu$vrq$1@cheetah.cadsoft.de...

"Ron" <Use@Forum.pls> a écrit dans le message de news:

foicn5$rug$1@cheetah.cadsoft.de...

"Guy" <guy.dau_no_spam@free.fr> wrote in message

news:fohqh1$sgn$1@cheetah.cadsoft.de...

Hi,

 

When I'm testing it I have just one DRC error with design rule

www.my4pcb.com you have select !!!

 

Guy

 

PS: I'm affray, you don't use any condensators on this card !!!

I think you must minimum add decouplers condensators to be sure work ok

!!!

Yes, that version had too tight of clearance for those 2 pins - I

corrected that already. Annoyed me, as when I auto routed that one trace

the DRC rules were not followed and I had to move the trace manually one

grid away from IC1. Luckily, there is a DRC check button!<smile>

 

Guy, this design (and the hand wired proto) definitely does not need VCC

bypass capacitors. It's a state machine, no clocking, and the USB module

(it's not a chip) includes its own decoupling to the USB buss; what that

module connects to is not powered by the USB buss and it is rather slow

and usually just sitting in one state. I do, however, need to (or should)

increase distance between the Power class traces. I gotta rip again

anyhow when I find out why freeDRM doesn't like the vias, I'll change the

class then.

-Ron

No !!

 

It's not because it's a state machine and no clocking then decoupling is

not necessary !!!

 

With all these circuits and not decoupling, alimentation can start in

resonance !!!

 

With many TTL and CMOS you don't know alimentation reaction !!

 

I think you must define any bypass/de-coupling and after perhaps not

necessary to put all but you don't know !!!!!

 

After many years of electronic developpement.......

 

Sorry for my english,

 

Guy

 

This is getting way off topic but I do respect and appreciate your usage of

English, please do not apologize. Although you could use a few less "!!!!!"

characters!!!!! <vbg> You are understandable and if the situation were

reversed I'd be, knowing only English, unable to return the courtesy.  But

most of all I respect your knowledge.

 

I would again try to qualify my agreement with what you say, which I believe

to be a reference to a phenomenon known as parasitic resonance and which is

a common annoyance in RF circuits. RF infers oscillation, and oscillating

circuits have maximum power response at a resonant frequency.  My point is

that there must be oscillation before there can be resonance, parasitic or

not. This occurs in digital circuits primarily because of repeating patterns

of current flow at high bit level changing rates (what I mean by "clocked",

be it data pattern repetition or any other time base). The capacitive

"decoupling" or "bypassing" is actually the detuning of the resonant

circuit, dampening the amplitude of unintended oscillations to negligible

level.  This is usually a very important consideration.

 

But, if my design works (and the prototype does) and it experiences

oscillations then it is malfunctioning because the amplitude of the

oscillation would have to be of sufficient energy as to overpower the power

supply as relates to the guaranteed high or low level specified for a gate

input. If the power supply is working and distributed properly then that

would have to be a rather huge amount of energy.  Without oscillation there

can be no resonance.  If there can be no resonance then decoupling is not

required.

 

In this board all I/O is inherently latched. Even when changing at USB 2.0

speed, the amount of time between cycles of a particular bit pattern that

just happens to be resonant is what keeps enough energy from entering the

tank to build sufficiently to overcome the power supply to a level where a

gate would see a logic change. There simply aren't enough such cycles within

a sufficiently small enough time period to build enough energy in a tank to

sustain oscillation. If Murphy gets into the act regardless, then the

mentioned time period can be lengthened by slowing down USB usage - thus

detuning the tank.

 

This board is an exception to the general rule that decoupling should be

used. Primarily because it is latched and not clocked by some means.

Repetitive tank pumping is not likely because repetitiveness does not exist

in a latched circuit like it does in a clocked circuit. It would not hurt to

use decoupling, except for production cost. My only worry with the entire

design is that I might be exceeding the fan out rating of the USB module. If

so, the resultant instability is not due to resonance or oscillation. On

this board decoupling would be of little use, malfunction must begin before

resonant oscillation can occur.

-Ron

 

 

Ron,

Even low speed logic circuitry can generate transient oscillations due

to the fast rise time of common digital ICs. This fast rise time causes

the power supply to "see" sharp changes in demand for power, giving

quite large voltage transients due to circuit inductance. This can

propagate to adjacent circuits. The bypass capacitor provides this

transient power to prevent or at least greatly reduce the spike on the

supply line. I think you are being too optimistic that all will be well,

just because the prototype worked OK.

If this is a production board, with many to be made, tolerances could

well give you a reasonable proportion which cause problems. It is

easier, and not very expensive to add bypass capacitors at the start.

John G.