Thermals on isolated vias

Thanks for the suggestion Robert.  I thought of that idea also, but I didn't

want to clutter the schematic with extraneous symbols.  But it looks like

that's the best solution for now.

Leo

"Robert" <rbeng@telenet.be> wrote in message

news:g2o5or$g66$1@cheetah.cadsoft.de...

Leo,

 

I recommend you add "Testpins" connected to GND in your schematic. That

way you will have single pad components on your PCB that you can place

anywhere in your GND polygons with thermals enabled. That way you don't

have to use vias as test points.

(Obviously this applies to any other signal where you want to add a test

point)

 

Robert

 

"Leo B" <leob001@gmail.com> wrote in message

news:g2m6o1$7cl$1@cheetah.cadsoft.de...

Gentlemen,

 

I've only been using Eagle for a few months on some simple two-sided

boards, and I'm not sure I understand all the comments here.  To clarify,

here's my situation:

 

I have a two-sided PCB with a ground plane on both sides  (a wide-band

high-gain video amp).  I use a large number of vias (without thermals) to

stitch the two ground planes together.  I want to use a couple of vias

for ground test points, thus the desire for thermals on these vias only.

It won't break my design if I can't do it - I can always find a big

soldering gun!   BTW I'm using Eagle 4.16r2.

 

Thanks for all the comments.

 

Leo B.

 

 

 

"Grzegorz Zalot" <complex@alpha.pl> wrote in message

news:g2lpl7$qmo$1@cheetah.cadsoft.de...

Hello T.Strothmann !:

...

 

Why argue with it?

 

Me ?????

 

The user has the control.

 

??????

 

It should be possible to set

the VIA characteristics in a way that it 1. disables thermal generation

regardless of other settings, 2. enables them regardless of other

settings, and 3. enables or disables them according to "Global Design

Rules" (note, NOT the DRC). Another nice example for this is the STOP

flag (see "Re: STOP flag, vias with and without stop mask" in

eagle.betatest) - same "ON - AUTO - OFF" scheme here. Once more: if at

all, such modifications need to be controlled by "Global Design Rules",

not by the "Design Rule Check".

 

Yes.

 

It's

about time to fix this terrible conceptual flaw!!

 

:-D ! IMHO last time ....

 

But the shortest way is possibility to disable the stupid global flag

for each polygon separately.

 

regards

--

Grzegorz Zalot

 

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

 

http://www.complex.org.pl/

Thanks for the suggestion Robert.  I thought of that idea also, but I didn't

want to clutter the schematic with extraneous symbols.  But it looks like

that's the best solution for now.

Leo

"Robert" <rbeng@telenet.be> wrote in message

news:g2o5or$g66$1@cheetah.cadsoft.de...

Leo,

 

I recommend you add "Testpins" connected to GND in your schematic. That

way you will have single pad components on your PCB that you can place

anywhere in your GND polygons with thermals enabled. That way you don't

have to use vias as test points.

(Obviously this applies to any other signal where you want to add a test

point)

 

Robert

 

"Leo B" <leob001@gmail.com> wrote in message

news:g2m6o1$7cl$1@cheetah.cadsoft.de...

Gentlemen,

 

I've only been using Eagle for a few months on some simple two-sided

boards, and I'm not sure I understand all the comments here.  To clarify,

here's my situation:

 

I have a two-sided PCB with a ground plane on both sides  (a wide-band

high-gain video amp).  I use a large number of vias (without thermals) to

stitch the two ground planes together.  I want to use a couple of vias

for ground test points, thus the desire for thermals on these vias only.

It won't break my design if I can't do it - I can always find a big

soldering gun!   BTW I'm using Eagle 4.16r2.

 

Thanks for all the comments.

 

Leo B.

 

 

 

"Grzegorz Zalot" <complex@alpha.pl> wrote in message

news:g2lpl7$qmo$1@cheetah.cadsoft.de...

Hello T.Strothmann !:

...

 

Why argue with it?

 

Me ?????

 

The user has the control.

 

??????

 

It should be possible to set

the VIA characteristics in a way that it 1. disables thermal generation

regardless of other settings, 2. enables them regardless of other

settings, and 3. enables or disables them according to "Global Design

Rules" (note, NOT the DRC). Another nice example for this is the STOP

flag (see "Re: STOP flag, vias with and without stop mask" in

eagle.betatest) - same "ON - AUTO - OFF" scheme here. Once more: if at

all, such modifications need to be controlled by "Global Design Rules",

not by the "Design Rule Check".

 

Yes.

 

It's

about time to fix this terrible conceptual flaw!!

 

:-D ! IMHO last time ....

 

But the shortest way is possibility to disable the stupid global flag

for each polygon separately.

 

regards

--

Grzegorz Zalot

 

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

 

http://www.complex.org.pl/