Thermals on isolated vias

Hello Leo B !:

Can anyone tell me how to apply thermals to isolated vias connecting ground

planes? 

You can use some restricts and ignore some errors. Unfortunately all

wires you should create manually. With small clearance you can use some

arcs in restrict layer.

Really the option "thermals" for polygons is quite stupid because the

general option for vias overwerites it ... only pads are affected.

I don't want to turn on "Generate thermals for vias" option in the

DRC. 

Why ????? This is IMHO best way to create good boards.

regards

--

Grzegorz Zalot

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

http://www.complex.org.pl/

"Grzegorz Zalot" <complex@alpha.pl> schrieb im Newsbeitrag

news:g2l6bc$qe4$1@cheetah.cadsoft.de...

Hello Leo B !:

Can anyone tell me how to apply thermals to isolated vias connecting

ground planes?

 

You can use some restricts and ignore some errors. Unfortunately all wires

you should create manually. With small clearance you can use some arcs in

restrict layer.

 

Really the option "thermals" for polygons is quite stupid because the

general option for vias overwerites it ... only pads are affected.

 

I don't want to turn on "Generate thermals for vias" option in the

DRC.

 

Why ????? This is IMHO best way to create good boards.

 

regards

--

Grzegorz Zalot

Why argue with it? The user has the control. It should be possible to set

the VIA characteristics in a way that it 1. disables thermal generation

regardless of other settings, 2. enables them regardless of other settings,

and 3. enables or disables them according to "Global Design Rules" (note,

NOT the DRC). Another nice example for this is the STOP flag (see "Re: STOP

flag, vias with and without stop mask" in eagle.betatest) - same "ON -

AUTO - OFF" scheme here. Once more: if at all, such modifications need to be

controlled by "Global Design Rules", not by the "Design Rule Check". It's

about time to fix this terrible conceptual flaw!!

T.

Hello T.Strothmann !:

...

Why argue with it?

Me ?????

The user has the control.

??????

It should be possible to set

the VIA characteristics in a way that it 1. disables thermal generation

regardless of other settings, 2. enables them regardless of other settings,

and 3. enables or disables them according to "Global Design Rules" (note,

NOT the DRC). Another nice example for this is the STOP flag (see "Re: STOP

flag, vias with and without stop mask" in eagle.betatest) - same "ON -

AUTO - OFF" scheme here. Once more: if at all, such modifications need to be

controlled by "Global Design Rules", not by the "Design Rule Check".

Yes.

It's

about time to fix this terrible conceptual flaw!!

:-D ! IMHO last time ....

But the shortest way is possibility to disable the stupid global flag

for each polygon separately.

regards

--

Grzegorz Zalot

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

http://www.complex.org.pl/

Gentlemen,

I've only been using Eagle for a few months on some simple two-sided boards,

and I'm not sure I understand all the comments here.  To clarify, here's my

situation:

I have a two-sided PCB with a ground plane on both sides  (a wide-band

high-gain video amp).  I use a large number of vias (without thermals) to

stitch the two ground planes together.  I want to use a couple of vias for

ground test points, thus the desire for thermals on these vias only.  It

won't break my design if I can't do it - I can always find a big soldering

gun!   BTW I'm using Eagle 4.16r2.

Thanks for all the comments.

Leo B.

"Grzegorz Zalot" <complex@alpha.pl> wrote in message

news:g2lpl7$qmo$1@cheetah.cadsoft.de...

Hello T.Strothmann !:

...

 

Why argue with it?

 

Me ?????

 

The user has the control.

 

??????

 

It should be possible to set

the VIA characteristics in a way that it 1. disables thermal generation

regardless of other settings, 2. enables them regardless of other

settings, and 3. enables or disables them according to "Global Design

Rules" (note, NOT the DRC). Another nice example for this is the STOP

flag (see "Re: STOP flag, vias with and without stop mask" in

eagle.betatest) - same "ON - AUTO - OFF" scheme here. Once more: if at

all, such modifications need to be controlled by "Global Design Rules",

not by the "Design Rule Check".

 

Yes.

 

It's

about time to fix this terrible conceptual flaw!!

 

:-D ! IMHO last time ....

 

But the shortest way is possibility to disable the stupid global flag for

each polygon separately.

 

regards

--

Grzegorz Zalot

 

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

 

http://www.complex.org.pl/

"Grzegorz Zalot" <complex@alpha.pl> wrote in message

news:g2lpl7$qmo$1@cheetah.cadsoft.de...

Hello T.Strothmann !:

...

 

Why argue with it?

 

Me ?????

Well, yes, you wrote "Why ????? This is IMHO best way to create good

boards.". And my opinion was that everybody has his personal preference on

how a good board should look like. My suggestion with the "improved via

control" gives you full flexibility in this respect, and as far as the

discussed problem is concerned.

The user has the control.

 

??????

Again: if you can't handle the described automatic actions in a

"ON-AUTO-OFF" fashion you don't have full control.

It should be possible to set

the VIA characteristics in a way that it 1. disables thermal generation

regardless of other settings, 2. enables them regardless of other

settings, and 3. enables or disables them according to "Global Design

Rules" (note, NOT the DRC). Another nice example for this is the STOP

flag (see "Re: STOP flag, vias with and without stop mask" in

eagle.betatest) - same "ON - AUTO - OFF" scheme here. Once more: if at

all, such modifications need to be controlled by "Global Design Rules",

not by the "Design Rule Check".

 

Yes.

 

It's about time to fix this terrible conceptual flaw!!

 

:-D ! IMHO last time ....

But the shortest way is possibility to disable the stupid global flag for

each polygon separately.

Yes, I agree - but in combination with the "ON-AUTO-OFF" setting of each

individual via!

T.

 

regards

--

Grzegorz Zalot

 

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

 

http://www.complex.org.pl/

"Leo B" <leob001@gmail.com> schrieb im Newsbeitrag

news:g2m6o1$7cl$1@cheetah.cadsoft.de...

Gentlemen,

 

I've only been using Eagle for a few months on some simple two-sided

boards, and I'm not sure I understand all the comments here.  To clarify,

here's my situation:

 

I have a two-sided PCB with a ground plane on both sides  (a wide-band

high-gain video amp).  I use a large number of vias (without thermals) to

stitch the two ground planes together.  I want to use a couple of vias for

ground test points, thus the desire for thermals on these vias only.  It

won't break my design if I can't do it - I can always find a big soldering

gun!   BTW I'm using Eagle 4.16r2.

 

Thanks for all the comments.

 

Leo B.

In short: no individual vias. There's only the global setting in the "DRC".

A workaround may be to specify devices with pads only, and use them as vias.

There's a different level of control for pads, local for each polygon.

T.

Leo,

I recommend you add "Testpins" connected to GND in your schematic. That way

you will have single pad components on your PCB that you can place anywhere

in your GND polygons with thermals enabled. That way you don't have to use

vias as test points.

(Obviously this applies to any other signal where you want to add a test

point)

Robert

"Leo B" <leob001@gmail.com> wrote in message

news:g2m6o1$7cl$1@cheetah.cadsoft.de...

Gentlemen,

 

I've only been using Eagle for a few months on some simple two-sided

boards, and I'm not sure I understand all the comments here.  To clarify,

here's my situation:

 

I have a two-sided PCB with a ground plane on both sides  (a wide-band

high-gain video amp).  I use a large number of vias (without thermals) to

stitch the two ground planes together.  I want to use a couple of vias for

ground test points, thus the desire for thermals on these vias only.  It

won't break my design if I can't do it - I can always find a big soldering

gun!   BTW I'm using Eagle 4.16r2.

 

Thanks for all the comments.

 

Leo B.

 

 

 

"Grzegorz Zalot" <complex@alpha.pl> wrote in message

news:g2lpl7$qmo$1@cheetah.cadsoft.de...

Hello T.Strothmann !:

...

 

Why argue with it?

 

Me ?????

 

The user has the control.

 

??????

 

It should be possible to set

the VIA characteristics in a way that it 1. disables thermal generation

regardless of other settings, 2. enables them regardless of other

settings, and 3. enables or disables them according to "Global Design

Rules" (note, NOT the DRC). Another nice example for this is the STOP

flag (see "Re: STOP flag, vias with and without stop mask" in

eagle.betatest) - same "ON - AUTO - OFF" scheme here. Once more: if at

all, such modifications need to be controlled by "Global Design Rules",

not by the "Design Rule Check".

 

Yes.

 

It's

about time to fix this terrible conceptual flaw!!

 

:-D ! IMHO last time ....

 

But the shortest way is possibility to disable the stupid global flag for

each polygon separately.

 

regards

--

Grzegorz Zalot

 

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

 

http://www.complex.org.pl/

"Robert" <rbeng@telenet.be> schrieb im Newsbeitrag

news:g2o5or$g66$1@cheetah.cadsoft.de...

Leo,

 

I recommend you add "Testpins" connected to GND in your schematic. That

way you will have single pad components on your PCB that you can place

anywhere in your GND polygons with thermals enabled. That way you don't

have to use vias as test points.

(Obviously this applies to any other signal where you want to add a test

point)

 

Robert

That's what I meant with the pad-only devices.

T.

P.S.: please don't post on top ("TOFU")

Thanks for the suggestion Robert.  I thought of that idea also, but I didn't

want to clutter the schematic with extraneous symbols.  But it looks like

that's the best solution for now.

Leo

"Robert" <rbeng@telenet.be> wrote in message

news:g2o5or$g66$1@cheetah.cadsoft.de...

Leo,

 

I recommend you add "Testpins" connected to GND in your schematic. That

way you will have single pad components on your PCB that you can place

anywhere in your GND polygons with thermals enabled. That way you don't

have to use vias as test points.

(Obviously this applies to any other signal where you want to add a test

point)

 

Robert

 

"Leo B" <leob001@gmail.com> wrote in message

news:g2m6o1$7cl$1@cheetah.cadsoft.de...

Gentlemen,

 

I've only been using Eagle for a few months on some simple two-sided

boards, and I'm not sure I understand all the comments here.  To clarify,

here's my situation:

 

I have a two-sided PCB with a ground plane on both sides  (a wide-band

high-gain video amp).  I use a large number of vias (without thermals) to

stitch the two ground planes together.  I want to use a couple of vias

for ground test points, thus the desire for thermals on these vias only.

It won't break my design if I can't do it - I can always find a big

soldering gun!   BTW I'm using Eagle 4.16r2.

 

Thanks for all the comments.

 

Leo B.

 

 

 

"Grzegorz Zalot" <complex@alpha.pl> wrote in message

news:g2lpl7$qmo$1@cheetah.cadsoft.de...

Hello T.Strothmann !:

...

 

Why argue with it?

 

Me ?????

 

The user has the control.

 

??????

 

It should be possible to set

the VIA characteristics in a way that it 1. disables thermal generation

regardless of other settings, 2. enables them regardless of other

settings, and 3. enables or disables them according to "Global Design

Rules" (note, NOT the DRC). Another nice example for this is the STOP

flag (see "Re: STOP flag, vias with and without stop mask" in

eagle.betatest) - same "ON - AUTO - OFF" scheme here. Once more: if at

all, such modifications need to be controlled by "Global Design Rules",

not by the "Design Rule Check".

 

Yes.

 

It's

about time to fix this terrible conceptual flaw!!

 

:-D ! IMHO last time ....

 

But the shortest way is possibility to disable the stupid global flag

for each polygon separately.

 

regards

--

Grzegorz Zalot

 

complex ltd.

office tel/fax : +48 32 2505840

mobil : +48 501 301515

 

http://www.complex.org.pl/

Leo B ha scritto:

Thanks for the suggestion Robert.  I thought of that idea also, but I didn't

want to clutter the schematic with extraneous symbols.  But it looks like

that's the best solution for now.

In my opinion you do have to show the test pins in the schematic. You

might want to know what you're testing...

Marco / iw2nzm