Eagle Standar 8 Layer StackUp

"Benjamin Maggi" <benjaminmaggi@gmail.com> wrote in message

news:2118566303.579701308860038421.JavaMail.jive@flcspu-csapp-01.premierfarnell.com...

Hi All,

 

Im trying to create an 8 Layer PCB stackup I want to follow the best

practices and I fond this site: http://www.hottconsultants.com along with

many other that say that my 8 layer board stackup should be make like this

(for better EMC and signal integrity)

 

~~~~~~~~~~~~~~~ Mounting Pads/Low Freq. Signals

:::::::::::::::::::::::::::::: Prepreg

+++++++++++++++ Pwr.

=============== FR4 Core

*------------------------------ * Gnd.

:::::::::::::::::::::::::::::: Prepreg

~~~~~~~~~~~~~~~ High Freq. Signals

=============== FR4 Core

~~~~~~~~~~~~~~~ High Freq. Signals

:::::::::::::::::::::::::::::: Prepreg

*------------------------------ * Gnd.

=============== FR4 Core

+++++++++++++++ Pwr.

:::::::::::::::::::::::::::::: Prepreg

~~~~~~~~~~~~~~~ Low Freq. Signals/Test Pads

 

I've never worked with eagle with so many layers, and never even bother

with blind and burried vias.

I need some help to define this stackup in eagle and also to create the

throu, burried and blind vias to connect the layers.

 

This is the very basic stackup I've with no vias

Image:eagle.jpg

Goto DRC (gui button), choose layers tab and enter: (12+345*67*16) in

setup box. Now you have the basics. You may enter layer thickness, but it

doesnt have much value unless you use microvias.

I have other prefs to signal assignment tho, but that all depends on usage

(signal types, speeds,...). This setup may have a lot of crosstalk between

inner layers if you route same direction, and power next to gnd is a waste

of silent planes imho.

I could give my suggestion if you say a bit more about the electronics you

want on it.

Hello Morten,

Thank you very much for your feedback.

The project I'm trying to develop is quite simply.

On one side of the board I've several shunt current sensors and on the other side I've a buffered output through a 74HC244 (tied to +5v) each of it's 8 outputs puts out a PWM frequency that is proportional to the current measured through the ADC, the range is not very high, from 0 to 1Mhz.

On the top you should see a step-down converter which works at around 15khz, and a bunch of other peripherals, SPI, UART, LED's.

On the center I've a microchip PIC33 doing all the hard work, clocked with a 20Mhz CX.

Initially I wanted just 4 layers, but I'm considering stepping it up to 8 to for better signal integrity and EMC, and because my 4 layer is a total mess!

A good designed could do the job with a 2 layer board, but not me, a good side effect of the 8 layer is better signal integrity and EMC characteristics and also I want better control of my routing so that I can scale up the prototype.

Using only through plated vias would be fine (1+2*3+4*5+6*7+16) I guess. the result is:

You can see the routing mess I've done in the picture:

Regards.

Ben.

"Benjamin Maggi" <communitymanager@premierfarnell.com> wrote in message

news:1794334828.581141308947556391.JavaMail.jive@flcspu-csapp-01.premierfarnell.com...

Hello Morten,

 

Thank you very much for your feedback.

 

The project I'm trying to develop is quite simply.

 

On one side of the board I've several shunt current sensors and on the

other side I've a buffered output through a 74HC244 (tied to +5v) each of

it's 8 outputs puts out a PWM frequency that is proportional to the

current measured through the ADC, the range is not very high, from 0 to

1Mhz.

 

On the top you should see a step-down converter which works at around

15khz, and a bunch of other peripherals, SPI, UART, LED's.

 

On the center I've a microchip PIC33 doing all the hard work, clocked with

a 20Mhz CX.

 

Initially I wanted just 4 layers, but I'm considering stepping it up to 8

to for better signal integrity and EMC, and because my 4 layer is a total

mess!

 

A good designed could do the job with a 2 layer board, but not me, a good

side effect of the 8 layer is better signal integrity and EMC

characteristics and also I want better control of my routing so that I can

scale up the prototype.

 

Using only through plated vias would be fine (1+234*567+16) I guess.

the result is:

Image:through.jpg

 

You can see the routing mess I've done in the picture:

Image:brd.jpg

First, a big boooo to element14 for image convertion to NNTP. They should at

least put an URL to the image on the root system.

Second, yes this looks like a 4 or 6 layer job. A microchip at 20Mhz doesnt

need very much routing care, but if you have buffers with very fast rise and

fall times, you should consider using slower for better EMC compatibility.

Also remember to put damper resistors on fast logic outputs. That stops a

lot of HF radiation.

I guess crosstalk isnt a big issue here at all, so I would just have one GND

layer and one power (maybe 1 layer shared if you have two voltages). If you

make the outer layers power (not exclusive;use polygons), you can bake in

the signals on the 4 inner layers and in some cases allow a track on outer.

Take care of exposed voltage pins when you make space for screws.

Also, take extra care of ESD protection on all your IO's, + be careful with

routing that critical switch mode regulator.

Its also possible you should reposition the components so that all multiwire

buses has a short distance, while single IO can go long distances.