"Via in Pad" not allowed? Tell me it ain't so!

Thanks all for the comments.  I would just get the yellow X and no via would appear.  DRC would then say there was no connection.  So I did manually place a via where I needed it and renamed it to the same net as one of you suggested.  I cannot follow why I would get an X when the via is at the terminus of routed traces on different layers, that seems like the perfect scenario, that's what you want, so why wouldn't a via be allowed there?

John,

The best way I've found to do the "stitch" is to open the library that contains the package and place small through hole pads in the D2PAK plane that you want to stitch.  You will have to add as many pins to the symbol as you have pads in the package, but then when you tie those to GND or whatever net you are stitching to in your schematic, and DRC is totally happy then, and they are then connected in the board.

Thanks all,

Stephen

On 12/11/2011 12:32 AM, Stephen Doll wrote:

Okay, I have a very tight layout.  Real estate on the board is premium.  I need to be able to run quite a few vias directly into a "same signal" pad on an SMD component.

 

Distance in DR's is set to 0 for same signal.

 

Board is set up to do this, but when I route to one of these points and try to place a via, I get the "big yellow X" instead.  I do not have blind and buried vias enabled (MicroVia set to 9.99mm) and this is a 6 layer board (12*314*15+16).  Via should go from layer 1 to 16, and works fine unless I try to put it at an SMD pad.

 

How do I get the editor to allow a Via In Pad?

 

Gone through the manual again..check.

Browsed the forums and found one where someone was asking about Via in Pad for BGA's, but when I try that solution, DRC has a conniption fit, and then I have one.......

 

Stephen

 

I have a similar situation where I put multiple vias in the large pad of

a D2PAK to "stitch" it to a power plane.  The DRC complains of "overlap"

even though they have the same signal name.  I haven't found a solution

other than to ignore the error.

On 12/11/2011 01:32 AM, Stephen Doll wrote:

Okay, I have a very tight layout.  Real estate on the board is

premium.  I need to be able to run quite a few vias directly into a

"same signal" pad on an SMD component.

 

Distance in DR's is set to 0 for same signal.

 

Board is set up to do this, but when I route to one of these points

and try to place a via, I get the "big yellow X" instead.

The yellow X tells you that the via is placed at the end of a route but

is not logically connected.  This also appears when routes on different

layers end at the same point.

After you place the via do a ratsnest.

HTH,

    - Chuck

Stephen Doll wrote:

Okay, I have a very tight layout. Real estate on the board is

premium. I need to be able to run quite a few vias directly into a

"same signal" pad on an SMD component.

 

Distance in DR's is set to 0 for same signal.

 

Board is set up to do this, but when I route to one of these points

and try to place a via, I get the "big yellow X" instead. I do not

have blind and buried vias enabled (MicroVia set to 9.99mm) and this

is a 6 layer board (12*314*15+16). Via should go from layer 1 to

16, and works fine unless I try to put it at an SMD pad.

 

How do I get the editor to allow a Via In Pad?

 

Gone through the manual again..check.

Browsed the forums and found one where someone was asking about Via

in Pad for BGA's, but when I try that solution, DRC has a conniption

fit, and then I have one.......

 

Stephen

If the via has the same name as the signal going to the pad and the minimum

clearance (DRC) for same signal SMD to Via is set to 0mil then there should

be no DRC error.

Which Eagle version are you using?

What are the DRC error you are getting

Warren

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