Actions
Forum Thread Details
  • Replies 4 replies
  • Subscribers 188 subscribers
  • Views 472 views
  • Users 0 members are here
Related

DRC vRestrict not honored in linux 5.1.0

holla2040

Folks,

The 5.1.0 manual page 145 says "vRestrict regions are not examined by the

DRC".

 

I'm creating a package with in-board heatsink with a top layer and bottom

layer poly regions connected via pads (TI called this a PowerPAD). I

surround my poly/pad setup with a vRestrict poly. The DRC reports clearance

errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

 

Is the page 145 description correct and I'm just doing something wrong?

 

Thanks,

Craig

ps. sorry for the cross-posting, I send the original to the wrong group.

 

 

 

Parents

  • Craig Hollabaugh schrieb:

    Folks,

    The 5.1.0 manual page 145 says "vRestrict regions are not examined by the

    DRC".

     

    I'm creating a package with in-board heatsink with a top layer and bottom

    layer poly regions connected via pads (TI called this a PowerPAD). I

    surround my poly/pad setup with a vRestrict poly. The DRC reports clearance

    errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

     

    Is the page 145 description correct and I'm just doing something wrong?

     

    The manual wants to say that the DRC does not check for vias that

    are placed inside the ViaRestrict area. Placing a via inside the

    area manually won't be indicated by an error message.

    Only the Autorouter will take care of such areas and won't

    place vias inside.

     

     

    --

    Mit freundlichen Gruessen / Best regards

    Richard Hammerl

      CadSoft Support -- hotline@cadsoft.de

      FAQ: http://www.cadsoft.de/faq.htm

     

Reply

  • Craig Hollabaugh schrieb:

    Folks,

    The 5.1.0 manual page 145 says "vRestrict regions are not examined by the

    DRC".

     

    I'm creating a package with in-board heatsink with a top layer and bottom

    layer poly regions connected via pads (TI called this a PowerPAD). I

    surround my poly/pad setup with a vRestrict poly. The DRC reports clearance

    errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

     

    Is the page 145 description correct and I'm just doing something wrong?

     

    The manual wants to say that the DRC does not check for vias that

    are placed inside the ViaRestrict area. Placing a via inside the

    area manually won't be indicated by an error message.

    Only the Autorouter will take care of such areas and won't

    place vias inside.

     

     

    --

    Mit freundlichen Gruessen / Best regards

    Richard Hammerl

      CadSoft Support -- hotline@cadsoft.de

      FAQ: http://www.cadsoft.de/faq.htm

     

Children
No Data