DRC vRestrict not honored in linux 5.1.0

Richard,

I'm confused. I asked this question about 8 years ago in 2008. Did you just answer this now, on April 7th? Or is there a problem with the e14 forum?

Is the answer still valid for the current version of eagle?

Craig

Craig Hollabaugh schrieb:

I'm creating a package with in-board heatsink with a top layer and

bottom

layer poly regions connected via pads (TI called this a PowerPAD). I

surround my poly/pad setup with a vRestrict poly. The DRC reports

clearance

errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

 

Is the page 145 description correct and I'm just doing something wrong?

The manual wants to say that the DRC does not check for vias that

are placed inside the ViaRestrict area. Placing a via inside the

area manually won't be indicated by an error message.

Only the Autorouter will take care of such areas and won't

place vias inside.

 

Richard,

Thanks for writing. I can't place vias within a package (or at least I don't

know how to). I think I can do all this on a board because I can assign a

signal to the top side poly, bottom side poly and the via then they're all

connected. However I can't figure out how to create these pieces within a

library package because I can't assign a signal to a poly or use vias. Do

you see my problem?

Craig

 

You said placing a manually placing a via the area won't generate an error

message if in vRestrict.

 

You misunderstood my words:

The vRestrict area can be used for the autorouter. If you draw this

area in the layout, the autorouter is not allowed to set vias inside.

In case you set vias manually in the layout and there is a vRestrict

area that covers the vias, the DRC does not complain about the vias

inside the vRestrict area.

Concerning package design:

You are right, there is no via command in the package editor. And it

is not possible to name, for example, polygons there.

But in some cases it is neccessary to use a polygon, for example,

for a special pad shape. In this case you can combine polygon and

Smds or Pads. But you will get an DRC error in the Layout which you

can approve then. There is no other solution at the moment.

--

Mit freundlichen Gruessen / Best regards

Richard Hammerl

  CadSoft Support -- hotline@cadsoft.de

  FAQ: http://www.cadsoft.de/faq.htm

I'm creating a package with in-board heatsink with a top layer and

bottom

layer poly regions connected via pads (TI called this a PowerPAD). I

surround my poly/pad setup with a vRestrict poly. The DRC reports

clearance

errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

 

Is the page 145 description correct and I'm just doing something wrong?

 

The manual wants to say that the DRC does not check for vias that

are placed inside the ViaRestrict area. Placing a via inside the

area manually won't be indicated by an error message.

Only the Autorouter will take care of such areas and won't

place vias inside.

Richard,

Thanks for writing. I can't place vias within a package (or at least I don't

know how to). I think I can do all this on a board because I can assign a

signal to the top side poly, bottom side poly and the via then they're all

connected. However I can't figure out how to create these pieces within a

library package because I can't assign a signal to a poly or use vias. Do

you see my problem?

Craig

You said placing a manually placing a via the area won't generate an error

message if in vRestrict.

Craig Hollabaugh schrieb:

Folks,

The 5.1.0 manual page 145 says "vRestrict regions are not examined by the

DRC".

 

I'm creating a package with in-board heatsink with a top layer and bottom

layer poly regions connected via pads (TI called this a PowerPAD). I

surround my poly/pad setup with a vRestrict poly. The DRC reports clearance

errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

 

Is the page 145 description correct and I'm just doing something wrong?

The manual wants to say that the DRC does not check for vias that

are placed inside the ViaRestrict area. Placing a via inside the

area manually won't be indicated by an error message.

Only the Autorouter will take care of such areas and won't

place vias inside.

--

Mit freundlichen Gruessen / Best regards

Richard Hammerl

  CadSoft Support -- hotline@cadsoft.de

  FAQ: http://www.cadsoft.de/faq.htm