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DRC vRestrict not honored in linux 5.1.0

holla2040

Folks,

The 5.1.0 manual page 145 says "vRestrict regions are not examined by the

DRC".

 

I'm creating a package with in-board heatsink with a top layer and bottom

layer poly regions connected via pads (TI called this a PowerPAD). I

surround my poly/pad setup with a vRestrict poly. The DRC reports clearance

errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

 

Is the page 145 description correct and I'm just doing something wrong?

 

Thanks,

Craig

ps. sorry for the cross-posting, I send the original to the wrong group.

 

 

 

Parents

  • I'm creating a package with in-board heatsink with a top layer and

    bottom

    layer poly regions connected via pads (TI called this a PowerPAD). I

    surround my poly/pad setup with a vRestrict poly. The DRC reports

    clearance

    errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

     

    Is the page 145 description correct and I'm just doing something wrong?

     

    The manual wants to say that the DRC does not check for vias that

    are placed inside the ViaRestrict area. Placing a via inside the

    area manually won't be indicated by an error message.

    Only the Autorouter will take care of such areas and won't

    place vias inside.

     

     

    Richard,

    Thanks for writing. I can't place vias within a package (or at least I don't

    know how to). I think I can do all this on a board because I can assign a

    signal to the top side poly, bottom side poly and the via then they're all

    connected. However I can't figure out how to create these pieces within a

    library package because I can't assign a signal to a poly or use vias. Do

    you see my problem?

    Craig

     

     

     

    You said placing a manually placing a via the area won't generate an error

    message if in vRestrict.

     

     

     

Reply

  • I'm creating a package with in-board heatsink with a top layer and

    bottom

    layer poly regions connected via pads (TI called this a PowerPAD). I

    surround my poly/pad setup with a vRestrict poly. The DRC reports

    clearance

    errors with the "DRC/Misc/Check Restrict" option enabled or disabled.

     

    Is the page 145 description correct and I'm just doing something wrong?

     

    The manual wants to say that the DRC does not check for vias that

    are placed inside the ViaRestrict area. Placing a via inside the

    area manually won't be indicated by an error message.

    Only the Autorouter will take care of such areas and won't

    place vias inside.

     

     

    Richard,

    Thanks for writing. I can't place vias within a package (or at least I don't

    know how to). I think I can do all this on a board because I can assign a

    signal to the top side poly, bottom side poly and the via then they're all

    connected. However I can't figure out how to create these pieces within a

    library package because I can't assign a signal to a poly or use vias. Do

    you see my problem?

    Craig

     

     

     

    You said placing a manually placing a via the area won't generate an error

    message if in vRestrict.

     

     

     

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