Does this ULP (Eagle 6.2 on a Mac) require the board to be configured for buried/blind vias ?
Whenever I run it, all that happens is that a dog-bone via is created and the signal is then routed out directly to the nearest edge. This works fine when there's no via in the way (from a closer-to-the-edge ball) but if there are multiple rows that need vias, it's completely useless.
Here's a picture of one such routed chip:
Ignoring that it failed to take into account the caps on the bottom side of the board, which I could live with, just running a DRC immediately after the "run route-bga U$1" command gives me 638 errors - there were 0 unapproved before the 'run...' command. Here's a close-up of what one part of the chip looks like:
I don't know what the problem is at D24,E24,... but clearly the problem for the via inside the {E22,E23,F22,F23} box is that it has E21 being routed *through* the via created for E22 to route out with. As far as I know, the only way that could work would be if the vias were generally expected to be blind.
Is this really the case ? I was hoping it would do a mini-autorouter kind of thing and find a way out for each via. This is a six-layer board, and given the "tracks" into the center formed by Vio/Vcc/Vdd I think it ought to be possible without blind vias. It's just damn annoying to keep on ripping up and retrying manually...
Simon
[ps: I can't get past the first page of the discussion, it just keeps saying "loading...", so apologies if this has been asked/answered before. There's no obvious discussion-specific search, either.]
