Issue on creating a pcb layout wth multple pcbs

On 2/3/2013 9:54 AM, Mario Brizida wrote:

Hi,

I made a project of a small pcb and then I want to create a board with multiple pcb's to produce my product.

When I used Eagle 6.3 I made following procedure without problems:

• Create a schematic in schematil layout editor.

• Design pcb with pcb layout editor linked with scheme.

• Made a copy of .brd file of my pcb.

• Opened copy file with pcb layout editor.

• Made a copy and paste of my pcb as many times I wanted in order co complete my board. All copies of my pcb were exact copies of original, in all layers.

 

When I use same procedure with Eagle 6.4, the layer tnames (25) has his content incremented (i.e. if I have in my original pcb 10 resistors named from R1 to R10, when I make a copy of my pcb, it presents same resistors with names R11 to R20. As I use layer 25 as data to my silkscreen, this is completely unacceptable. How can I make Eagle 6.4 work in this case as Eagle 6.3?

 

Thanks

 

Hi Mario,

It seems you forgot to run the panelize.ulp which copies the silkscreen

to new layers as plain text. Then instead of using the normal silkscreen

layers for gerber output you use the ones generated by the panelize.ulp.

In this respect 6.4 is no different that 6.3 so it means the difference

probably lies in omitting the panelize.ulp in your procedure.

Let me know if there's anything else I can do for you.

Best Regards,

Jorge Garcia

On 2/3/2013 9:54 AM, Mario Brizida wrote:

Hi,

I made a project of a small pcb and then I want to create a board with multiple pcb's to produce my product.

When I used Eagle 6.3 I made following procedure without problems:

• Create a schematic in schematil layout editor.

• Design pcb with pcb layout editor linked with scheme.

• Made a copy of .brd file of my pcb.

• Opened copy file with pcb layout editor.

• Made a copy and paste of my pcb as many times I wanted in order co complete my board. All copies of my pcb were exact copies of original, in all layers.

 

When I use same procedure with Eagle 6.4, the layer tnames (25) has his content incremented (i.e. if I have in my original pcb 10 resistors named from R1 to R10, when I make a copy of my pcb, it presents same resistors with names R11 to R20. As I use layer 25 as data to my silkscreen, this is completely unacceptable. How can I make Eagle 6.4 work in this case as Eagle 6.3?

 

Thanks

 

Hi Mario,

It seems you forgot to run the panelize.ulp which copies the silkscreen

to new layers as plain text. Then instead of using the normal silkscreen

layers for gerber output you use the ones generated by the panelize.ulp.

In this respect 6.4 is no different that 6.3 so it means the difference

probably lies in omitting the panelize.ulp in your procedure.

Let me know if there's anything else I can do for you.

Best Regards,

Jorge Garcia