Hello.
After I read several postings about multilayer board, via, clearance,
etc from this newsgroup, I have got some questions about via restring
and clearance to the ground plane.
I want to create 6 layer board with Eagle as the following layer
configuration.
1 - signal
2 - ground
3 - signal
4 - vcc ( 3.3V, 2.5V, 1.2V )
5 - ground
15 - signal
According to Martin's Q&A, "6 layer board and 2 GND supply planes"
at 2007/11/08, defining two ground plane as supply layer is not allowed.
So I have to create ground layer(2 & 5) with a polygon.
In addition, as layer 4 has multiple nets, I have to create vcc layer(4)
with polygons.
Now, if a via is connected from the layer 15(signal) to layer 3(signal),
according to Tomas Pribyl's Q&A, "Via on 4-layers PCB" at 2006/06/02,
"pad of via and isolation gap are generated even if via is not connected to
GND or VCC". Therefore, it will create the large gap in layer 5(ground)
and layer 4(vcc) in my case. Sadly, annulus isolate or gap settings
at supply tab in the DRC settings has no effect on polygon-created
supply layer. (It works only on the supply layer.)
The answer to the question was to set the via inner layer
restring to zero in the DRC settings. It will work fine for ground and vcc
layer. But, the problem is in layer 3(signal). layer 3 can't have
the restring at all because via inner layer restring is set to zero.
The question,
1) Is there any ways to make annulus isolate DRC setting work on
polygon-created supply layer?
2) is there any ways to make two different inner layer have two different
via
restring?
Thanks in advance.
Best regards.
--
Taeho Oh ( ohhara@postech.edu , ohhara@plus.or.kr )
Postech ( Pohang University of Science and Technology )
Digital Media Professionals Inc.
