Adding despiking capacitors

I'm just here to wax logorrheic 'bout decoupling.  Logic gates are amplifiers.  Old guys such as myself remember putting unbuffered silicon-gate CMOS jellybeans in the feedback path of op-amps in order to effectuate RRIO before. . .I digress.

One of my wonderful teachers had me attacking a pile of audio amps from the fifties during the eighties.  By and large, their defect was that they were 'motor-boating.'  What happened was that the 'lytics bulking up the supply had gone dry.  Now the supply was providing phase lag, basically saying 'yup, I'll get on it!' when the amp told it to move.  Barkhausen was right.  180 degrees + gain above unity -> oscillations, intended or not.  All oscillators obey f(x)-f''(x)=0, I digress.  They put me on this task in hopes that I could develop my intuition beyond the page.  Nice to them to try.

For clarity, logic schematics don't illustrate the return path, typically.  They have magical ground labels.  But the ground trace is actually made out of tinned Cu, not magical fairy dust.

That said, the impact of the decouplers isn't all good.  We have to consider the inrush event.  We may consider placing a backwards diode across our regulator to protect it during power-off.  I will re-emphasize that the local filters must be local to the devices intended to be served.  R and or L in the path practically removes them.  We are also possibly making a resonant tank with our power trace inductance.

A device that calls itself a capacitor has a frequency of first resonance, above which, at least for awhile it is an inductor.  This is when the parasitic inductances become more significant than the capacitance.

A device that calls itself an inductor has a frequency of first resonance, above which, at least for awhile (frequency analogy to time) parasitic capacitances whelm the inductance.

I digress.

A chip that uses more current or is faster usually needs more decoupling.

A voltage comparator chip may need atypically great decoupling relative to a similarly-constructed logic chip, because our voltage error margin is less.  This goes doubly for A/D converters of greater n.  Or maybe moreso.

True to say 'strange issues.'  Be on the lookout for lost decoupling during repair.  This will impose a phase lag that will be more deleterious to fast signals, high current signals may crap-out in a characteristic manner.

People sometimes try to use 'lytics here, which is IMHO a mistake for high-speed circuitry.  If you disagree with me, please be gentle, but they just, often, aren't fast enough.

You can, if you have room, make helpful decouplers on a multi-layer board by using the power planes under the chip, this doesn't replace physical parts, but it helps.  Let me say, generally, when designing circuit boards, don't etch copper unnecessarily!  Environmental motives alone are compelling in this, I digress. . .

Current considerations run in parallel here:  Supply traces should be thicker than signal traces, sometimes to the point of employing bus-bars.

Try to Q-spoil your supply layout as well.

Another controversy on this topic is bead speed.  I like a slow bead, because I want it to dissipate AC as heat.  Others insist on a fast bead, I think because they believe they are easier to model, to my mind that is upon the outskirts of Q-city, a near-neighbor to Pallokaville.  I like to throw in a tiny fuse, often, but I might be a fuss-budget.

I'm just here to wax logorrheic 'bout decoupling.  Logic gates are amplifiers.  Old guys such as myself remember putting unbuffered silicon-gate CMOS jellybeans in the feedback path of op-amps in order to effectuate RRIO before. . .I digress.

One of my wonderful teachers had me attacking a pile of audio amps from the fifties during the eighties.  By and large, their defect was that they were 'motor-boating.'  What happened was that the 'lytics bulking up the supply had gone dry.  Now the supply was providing phase lag, basically saying 'yup, I'll get on it!' when the amp told it to move.  Barkhausen was right.  180 degrees + gain above unity -> oscillations, intended or not.  All oscillators obey f(x)-f''(x)=0, I digress.  They put me on this task in hopes that I could develop my intuition beyond the page.  Nice to them to try.

For clarity, logic schematics don't illustrate the return path, typically.  They have magical ground labels.  But the ground trace is actually made out of tinned Cu, not magical fairy dust.

That said, the impact of the decouplers isn't all good.  We have to consider the inrush event.  We may consider placing a backwards diode across our regulator to protect it during power-off.  I will re-emphasize that the local filters must be local to the devices intended to be served.  R and or L in the path practically removes them.  We are also possibly making a resonant tank with our power trace inductance.

A device that calls itself a capacitor has a frequency of first resonance, above which, at least for awhile it is an inductor.  This is when the parasitic inductances become more significant than the capacitance.

A device that calls itself an inductor has a frequency of first resonance, above which, at least for awhile (frequency analogy to time) parasitic capacitances whelm the inductance.

I digress.

A chip that uses more current or is faster usually needs more decoupling.

A voltage comparator chip may need atypically great decoupling relative to a similarly-constructed logic chip, because our voltage error margin is less.  This goes doubly for A/D converters of greater n.  Or maybe moreso.

True to say 'strange issues.'  Be on the lookout for lost decoupling during repair.  This will impose a phase lag that will be more deleterious to fast signals, high current signals may crap-out in a characteristic manner.

People sometimes try to use 'lytics here, which is IMHO a mistake for high-speed circuitry.  If you disagree with me, please be gentle, but they just, often, aren't fast enough.

You can, if you have room, make helpful decouplers on a multi-layer board by using the power planes under the chip, this doesn't replace physical parts, but it helps.  Let me say, generally, when designing circuit boards, don't etch copper unnecessarily!  Environmental motives alone are compelling in this, I digress. . .

Current considerations run in parallel here:  Supply traces should be thicker than signal traces, sometimes to the point of employing bus-bars.

Try to Q-spoil your supply layout as well.

Another controversy on this topic is bead speed.  I like a slow bead, because I want it to dissipate AC as heat.  Others insist on a fast bead, I think because they believe they are easier to model, to my mind that is upon the outskirts of Q-city, a near-neighbor to Pallokaville.  I like to throw in a tiny fuse, often, but I might be a fuss-budget.

"People sometimes try to use 'lytics here, which is IMHO a mistake for high-speed circuitry.  If you disagree with me, please be gentle, but they just, often, aren't fast enough."

No, I agree.  Electrolytics tend to have a large inductive component, so are lousy for absorbing transition spikes which typically have frequency components that appear as high impedance at the inductance of a typical electrolytic.

"You can, if you have room, make helpful decouplers on a multi-layer board by using the power planes under the chip,"

I doubt there would be enough capacitance to make a difference in most cases.

"Supply traces should be thicker than signal traces, sometimes to the point of employing bus-bars."

Supply traces should be thick enough to deliver the peak current without critical voltage loss ["critical" is defined by the application].  Signal traces can, typically, be smaller [as most signals are conveyed with little or no current], but they don't have to be.  They, can, in fact, be as large as the supply traces -- if there is room.  And, in fact, this would come closer to satisfying the "don't etch copper unnecessarily" rule.

Decoupling is required on devices that generate current spikes when transitioning.  The totem-pole outputs on TTL devices cause substantial current spikes because as they transition from 1 to 0 or vice-versa, there is a short period where both the upper and lower transistor is on, thus providing a low impedance path from supply to ground.  This is less of an issue in CMOS devices -- and that's the extent of my knowledge--as I'm sure there is nuance in the many other logic families and such.  The despiking capacitor must behave like a capacitor at the frequencies produced by the spike AND must store enough energy to supply enough current during the transition so that current isn't pulled from the supply line.  The resistance path from the capacitor to the logic device must be low enough for the RC time constant to be faster than the frequencies involved AND the impedance through that same path must be low enough to allow the full spike current to flow from the capacitor to the IC AND the resonant frequency of the tank circuit created by the two series inductors created by the traces and the capacitance of the despiking capacitor must be much higher than the highest circuit frequency.  This is why the despiking capacitor needs to be close to the logic device -- because the traces, like all wires, act like inductors and if too long, will have an inductance that presents a high impedance path between the capacitor and the logic device.  And, in fact, ringing can occur, making the problem worse.  Because the traces are inductors, they, in concert with the capacitor, produce a tank circuit.

I learned about the importance of despiking capacitors from the failure experienced by a friend of mine.  He prototyped an elaborate TTL circuit and it acted nothing like what he intended.  It had numerous counters that kept skipping counts and flip-flop states that kept transitioning when they shouldn't - it was a real mess.

This was back when TTL brand new and strange -- we hit the books and finally learned about despiking capacitors.  After a liberal dusting, it started acting better, producing, nearly the intended result.  Soon after that, we learned about synchronous counters -- heck we were just a couple of teenagers--what did we know