Adding despiking capacitors

You can add these capacitors in the schematic like you would add any other part and connect them to the chip the way you would connect any other parts.  On the schematic, it doesn't matter where you place the capacitors physically, but they should be connected directly to the chip electrically.  When you make your board, then you can place the parts very close together.

The INVOKE command is used for the chips themselves and allows you to place part of the chip on your schematic.  For example, if you have a quad op amp, you can invoke any of the four op amp circuits.  If you don't use one or more of the op amps, you don't have to invoke them and they won't show on the schematic.

Doug is quite correct about the 'despiking caps' and placement.

In addition adding one (0.1uF) close to the regulator or incoming source of power is good practice, and any larger value capacitors 10-10,000uF should be closer to the regulator or incoming power source.

It great to see you adding them, we often see issues where people haven't added them and then have strange issues.

Mark

I'm just here to wax logorrheic 'bout decoupling.  Logic gates are amplifiers.  Old guys such as myself remember putting unbuffered silicon-gate CMOS jellybeans in the feedback path of op-amps in order to effectuate RRIO before. . .I digress.

One of my wonderful teachers had me attacking a pile of audio amps from the fifties during the eighties.  By and large, their defect was that they were 'motor-boating.'  What happened was that the 'lytics bulking up the supply had gone dry.  Now the supply was providing phase lag, basically saying 'yup, I'll get on it!' when the amp told it to move.  Barkhausen was right.  180 degrees + gain above unity -> oscillations, intended or not.  All oscillators obey f(x)-f''(x)=0, I digress.  They put me on this task in hopes that I could develop my intuition beyond the page.  Nice to them to try.

For clarity, logic schematics don't illustrate the return path, typically.  They have magical ground labels.  But the ground trace is actually made out of tinned Cu, not magical fairy dust.

That said, the impact of the decouplers isn't all good.  We have to consider the inrush event.  We may consider placing a backwards diode across our regulator to protect it during power-off.  I will re-emphasize that the local filters must be local to the devices intended to be served.  R and or L in the path practically removes them.  We are also possibly making a resonant tank with our power trace inductance.

A device that calls itself a capacitor has a frequency of first resonance, above which, at least for awhile it is an inductor.  This is when the parasitic inductances become more significant than the capacitance.

A device that calls itself an inductor has a frequency of first resonance, above which, at least for awhile (frequency analogy to time) parasitic capacitances whelm the inductance.

I digress.

A chip that uses more current or is faster usually needs more decoupling.

A voltage comparator chip may need atypically great decoupling relative to a similarly-constructed logic chip, because our voltage error margin is less.  This goes doubly for A/D converters of greater n.  Or maybe moreso.

True to say 'strange issues.'  Be on the lookout for lost decoupling during repair.  This will impose a phase lag that will be more deleterious to fast signals, high current signals may crap-out in a characteristic manner.

People sometimes try to use 'lytics here, which is IMHO a mistake for high-speed circuitry.  If you disagree with me, please be gentle, but they just, often, aren't fast enough.

You can, if you have room, make helpful decouplers on a multi-layer board by using the power planes under the chip, this doesn't replace physical parts, but it helps.  Let me say, generally, when designing circuit boards, don't etch copper unnecessarily!  Environmental motives alone are compelling in this, I digress. . .

Current considerations run in parallel here:  Supply traces should be thicker than signal traces, sometimes to the point of employing bus-bars.

Try to Q-spoil your supply layout as well.

Another controversy on this topic is bead speed.  I like a slow bead, because I want it to dissipate AC as heat.  Others insist on a fast bead, I think because they believe they are easier to model, to my mind that is upon the outskirts of Q-city, a near-neighbor to Pallokaville.  I like to throw in a tiny fuse, often, but I might be a fuss-budget.

Edit.  Herr Barkhausen actually states that we need 360 degrees of phase lag and loop gain greater than unity..  It's late, I hurry, I can be a bit of a dummy.

Good stuff to think about.  I was going to call you out on the 180 degree thing, but you beat me to it.  LOL!

Dear Don Hersey,  mcb1 + Doug Wellington,

Wow!!!! Very fast and awesome response!! Thank you so much gentlemen. Yes, very correct, one just has to place them in the schematic and then later move them closer to the chips. I am now after I read the insight on, "over use" of these caps........thinking of.......instead of one cap per chip, perhaps will use......one cap per two chips. It is very easy to overdo this decoupling/despiking thing. The currents will start to breath instead of flow on the tracks.

I am designing my power tracks 3 times ticker then my signal tracks also, much better for the overall impedance.

Thx again gentlemen!

Cheers,

peter

Yes it is possible to "over decouple" your supply by having too many large capacitors  however it's generally better to have many small (say0.1uf) capacitors by every chip than having a larger one every so often. Each small capacitor supplies decoupling to each chip in turn which is what you are after!

Decoupling caps actually provide 2 services - most people think they help

keep the power clean to the logic chips.  That is true, HOWEVER, they also

are there to prevent the logic chips from putting their switching noise

back on the power line for the other chips.  Many people look at from the

standpoint of if the power is clean, then everything on the board will be

fine and forget that switching transients from different families of logic

can be pretty nasty.  TTL used to have a bunch of issues like that (but I

date myself ... )

mikey

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mikey

You are so correct.

I guess as old timers we remember our training and sort of jump to the end ..ie a clean power supply.

Knowing that to have a clean power supply you have removed the mains/switching ripple at the supply, then removed the switching transients caused by the logic (or other) again at the source.

We've also ignored that we know the appropriate type of capacitor to use for each instance.

Thanks for reminding me to not overlook the bits that became ingrained during our training.

Mark

Ah the old days of 100 mixed chips on a wirewrapped card.  We frantically

sprinkled 0.1ufd ceramic caps all over the place (remember the IC sockets

with the 0.1ufd caps in them?).  Without proper bypassing, you could spend

weeks trying to troubleshoot a board only to discover the issue was

switching transients causing all your problems.  Didn't have these issues

with vacuum tubes, but I do remember getting some nasty shocks poking

around in there

mikey

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