element14 Community
element14 Community
    Register Log In
  • Site
  • Search
  • Log In Register
  • Community Hub
    Community Hub
    • What's New on element14
    • Feedback and Support
    • Benefits of Membership
    • Personal Blogs
    • Members Area
    • Achievement Levels
  • Learn
    Learn
    • Ask an Expert
    • eBooks
    • element14 presents
    • Learning Center
    • Tech Spotlight
    • STEM Academy
    • Webinars, Training and Events
    • Learning Groups
  • Technologies
    Technologies
    • 3D Printing
    • FPGA
    • Industrial Automation
    • Internet of Things
    • Power & Energy
    • Sensors
    • Technology Groups
  • Challenges & Projects
    Challenges & Projects
    • Design Challenges
    • element14 presents Projects
    • Project14
    • Arduino Projects
    • Raspberry Pi Projects
    • Project Groups
  • Products
    Products
    • Arduino
    • Avnet & Tria Boards Community
    • Dev Tools
    • Manufacturers
    • Multicomp Pro
    • Product Groups
    • Raspberry Pi
    • RoadTests & Reviews
  • About Us
  • Store
    Store
    • Visit Your Store
    • Choose another store...
      • Europe
      •  Austria (German)
      •  Belgium (Dutch, French)
      •  Bulgaria (Bulgarian)
      •  Czech Republic (Czech)
      •  Denmark (Danish)
      •  Estonia (Estonian)
      •  Finland (Finnish)
      •  France (French)
      •  Germany (German)
      •  Hungary (Hungarian)
      •  Ireland
      •  Israel
      •  Italy (Italian)
      •  Latvia (Latvian)
      •  
      •  Lithuania (Lithuanian)
      •  Netherlands (Dutch)
      •  Norway (Norwegian)
      •  Poland (Polish)
      •  Portugal (Portuguese)
      •  Romania (Romanian)
      •  Russia (Russian)
      •  Slovakia (Slovak)
      •  Slovenia (Slovenian)
      •  Spain (Spanish)
      •  Sweden (Swedish)
      •  Switzerland(German, French)
      •  Turkey (Turkish)
      •  United Kingdom
      • Asia Pacific
      •  Australia
      •  China
      •  Hong Kong
      •  India
      • Japan
      •  Korea (Korean)
      •  Malaysia
      •  New Zealand
      •  Philippines
      •  Singapore
      •  Taiwan
      •  Thailand (Thai)
      • Vietnam
      • Americas
      •  Brazil (Portuguese)
      •  Canada
      •  Mexico (Spanish)
      •  United States
      Can't find the country/region you're looking for? Visit our export site or find a local distributor.
  • Translate
  • Profile
  • Settings
Autodesk EAGLE
  • Products
  • More
Autodesk EAGLE
EAGLE User Support (English) No error reported on via in vrestrict (layer43) polygon !
  • Blog
  • Forum
  • Documents
  • Events
  • Polls
  • Files
  • Members
  • Mentions
  • Sub-Groups
  • Tags
  • More
  • Cancel
  • New
Join Autodesk EAGLE to participate - click to join for free!
Actions
  • Share
  • More
  • Cancel
Forum Thread Details
  • State Verified Answer
  • Replies 3 replies
  • Subscribers 178 subscribers
  • Views 688 views
  • Users 0 members are here
Related

No error reported on via in vrestrict (layer43) polygon !

kikoun
kikoun over 11 years ago

Hi,

 

On some package I add a vRestric (layer 43) polygon because I want to be sure that there will be no via (or holes) in this area.

But it seems that when I put a via in the area, there is no DRC error or warning !!!!

How can I activate this checking ???? (I hope it's possible !)

I already activate the 'Check restrict' in 'Misc' tab in the DRC setting.

 

Guillaume Barrey 

  • Sign in to reply
  • Cancel
  • kikoun
    0 kikoun over 11 years ago

    No body have a clue ?

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • autodeskguest
    0 autodeskguest over 11 years ago in reply to kikoun

    Guillaume barrey[1

    wrote on Wed, 05 November 2014 02:52]No body have a clue ?

     

     

    EAGLE won't give you an error if a via is placed in a rectangle or other

    shape on that layer.  All it does is restrict the auto-router from placing

    a via in that layer.

     

    Of course that is silly and really negates the point of the layer. 

    CadSoft should change this, or at least give an option for the vrestrict

    layer to actually create an error if a via is within that area.  That is

    what any rational person would think it does and it's actually a needed

    function.

     

    From the help for the RECT command

     

     

    If used in the layers tRestrict, bRestrict, or vRestrict, the RECT command

    defines restricted areas for the Autorouter.

     

     

    This isn't 100% true.  For tRestrict and bRestrict it will also create DRC

    errors if there is copper in those areas.  But vRestrict works differently.

    This is a bug and should be fixed.

     

    In addition, there is probably more nuanced control that is needed for

    blind and buried vias.  If you're trying to make sure that a via wouldn't

    short to the bottom of a connector (for instance) then it's OK if you have

    a via in that location as long as it doesn't come out to the surface.

     

    And while we're at it, being able to identify a restrict area on an inner

    layer is often needed as well.  For instance, under the antenna of an RF

    module.  Some nuance here because you'd want to put that into the footprint

    of a part to cover all layers but not all boards have all layers.  So that

    needs to be considered.

     

    So in general, I'd like to see a lot more improvement in the restrict

    methodology.  But yes, at a bare minimum vRestrict should give DRC errors

    when a via is placed in that area.

     

    James.

    --

    James Morrison  ~~~  Stratford Digital

     

    Specializing in CadSoft EAGLE

    • Online Sales to North America

    • Electronic Design Services

     

    Take advantage of v7 License Promotion right now at

    http://www.eaglecentral.ca

    --

    Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

     

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Reject Answer
    • Cancel
  • kikoun
    0 kikoun over 11 years ago in reply to autodeskguest

    Hello,

     

    Ok then, it's not a bug, it's a missing feature !

    And I'm thinking 100% like James !

    - drc error on via/hole restriction area is a "must" or this layer is useless (except for auto router, but what the point of letting the user do something the auto-router is not allowed to do !)

     

    - For buried/bling via, a first simple solution is to report a error for ALL kind of via, and the user can approve the error... but the best would be to take buried/blind via into account when we design a Polygon in restricted area.

    Maybe, the polygons in this layer should have some specifics parameters like the list of copper layer to which the restriction applies (in the case of a polygon in this vrestric layer, that would be more useful than the 'isolate' parameter!!!)

    This parameter could be working like the display command :

         "ALL"  - > apply to all copper layer.

         "NONE 16"  -> apply to bottom only.

         "bottom 15 ??" apply to bottom, and layer 15 if this layer is present

         ....

     

    - restrict for inner layer is missing too. And in order to manage present/missing layer on each board.... why don't using the same approach ! A parameter in the polygon command, to select the layer(s) to restrict, and don't worried about missing layer ! (use the "??", like in the display command). In that case, Only one of the 2 layers (tRestrict and bRestrict) is necessary !

     

    Maybe this post should be move in the "suggestion" forum....

     

    Guillaume Barrey

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
element14 Community

element14 is the first online community specifically for engineers. Connect with your peers and get expert answers to your questions.

  • Members
  • Learn
  • Technologies
  • Challenges & Projects
  • Products
  • Store
  • About Us
  • Feedback & Support
  • FAQs
  • Terms of Use
  • Privacy Policy
  • Legal and Copyright Notices
  • Sitemap
  • Cookies

An Avnet Company © 2025 Premier Farnell Limited. All Rights Reserved.

Premier Farnell Ltd, registered in England and Wales (no 00876412), registered office: Farnell House, Forge Lane, Leeds LS12 2NE.

ICP 备案号 10220084.

Follow element14

  • X
  • Facebook
  • linkedin
  • YouTube