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EAGLE User Support (English) How does one remove non-functional pads in vias?
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Forum Thread Details
  • State Suggested Answer
  • Replies 9 replies
  • Answers 2 answers
  • Subscribers 181 subscribers
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  • capture
  • pad
  • discontinuities
  • stack
  • non-functional
  • restring
  • impedance
  • removal
  • via
  • routing
Related

How does one remove non-functional pads in vias?

Former Member
Former Member over 10 years ago

How does one remove non-functional pads in vias?  I’m not finding the requisite check box(es) or other settings. 

I need to minimize the discontinuities in at least the higher frequency paths, want to somewhat shrink the resulting anti-pads on the ground and supply layers to improve current return impedance, and it can often contribute to better routing in the vicinity of vias.

I was hoping to even set it by layer and perhaps set the restring by layer, having it depend upon whether there is a trace connected or not.

The only alternative seems labor-crazy intensive, effectively:

  • Setting normal via restring values and applying the appropriate teardrops to the various layers
  • Minimize the restring values to the smallest NFP values wanted for the board, and
  • apply a circle to each and every capture pad where there is a trace to be connected
  • subsequently approving the circle overlap DRC errors

Please describe a better way…?

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  • autodeskguest
    autodeskguest over 8 years ago in reply to gcourtney +1
    On 6/15/2017 10:33 AM, Glenn Courtney wrote: To your knowledge has this situation changed as far as the toll itself goes? Did you get anywhere with a viable work around? Thanks -- To view any images and…
Parents
  • autodeskguest
    0 autodeskguest over 10 years ago

    On 12/04/2015 2:33 a.m., Bruce Mellen wrote:

    How does one remove non-functional pads in vias?  I’m not finding the

    requisite check box(es) or other settings.

    I need to minimize the discontinuities in at least the higher frequency

    paths, want to somewhat shrink the resulting anti-pads on the ground and

    supply layers to improve current return impedance, and it can often

    contribute to better routing in the vicinity of vias.

    I was hoping to even set it by layer and perhaps set the restring by

    layer, having it depend upon whether there is a trace connected or not.

    The only alternative seems labor-crazy intensive, effectively:

    • Setting normal via restring values and applying the appropriate

    teardrops to the various layers

    • Minimize the restring values to the smallest NFP values wanted for the

    board, and

    • apply a circle to each and every capture pad where there is a trace to

    be connected

    • subsequently approving the circle overlap DRC errors

    Please describe a better way…?

     

    --

    To view any images and attachments in this post, visit:

    http://www.element14.com/community/message/146824

     

     

     

    So you mean " How does one remove the unused restrings from the inner

    layers"

     

    This is all about 'pad stacks' and the ability to specify the restring

    by layer or even pad/via. Historically this feature was requested many

    times and has not been delivered by Cadsoft. Jorge did mention recently

    that they were working on keep-outs for the inner layers so perhaps that

    implies pad stacks are coming. As an aside; I note that many of the

    power users who were vocal about their need for pad stacks either are

    known to have moved away from eagle or are not heard from very often

    these days suggesting they have voted with their feet.

     

    You may care to investigate the following ideas:

    (1) Edit/delete these unwanted restrings in your Gerber editor.

    (2) Don't place the circle, that you subsequently have to approve in the

    DRC, on the signal layer but rather on a user defined non signal layers

    and merge the signal and non signal layer when you generate the Gerber

    for that copper/signal layer.

    (3) Create a ULP to automate the 'labor-crazy' part. Again, start as you

    have with minimised inner restrings. Use the ULP to locate the inner

    restrings that have traces connected. The ULP then adds a polygon

    (circle) over that restring of the required size. The polygon is given

    the same signal name as the trace so there are no DRC errors.

     

    HTH

    Warren

     

     

     

     

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  • Former Member
    0 Former Member over 10 years ago in reply to autodeskguest

    Warren,

    Thanks for the potential workarounds; I understand what you are describing.  My knowledge of ULP and the data structures, however, is non-existent. 

     

    It appears that the product is not quite ready to do the serious work I was hoping to occasionally do.

     

    You gave me an idea….. What might be an even better workaround might be: for the person that does the teardropsc URL (helpful in preventing breakout with drill wander and providing a more secure connection to vias), to also include an arc (of the same signal) that mostly surrounds the hole, with each end of the arc at the teardrop intersections with the capture pad.  After teardropsc is run as one of the last steps before generating Gerbers, the inner restring value can then be minimized.  The snippet below shows what might result in an inner layer – being just my curved trace, two short traces, and three arcs, to cover the area that needs to be occupied by the normal restring capture pad.  The via hole is the circle in the center.image

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  • Former Member
    0 Former Member over 10 years ago in reply to autodeskguest

    Warren,

    Thanks for the potential workarounds; I understand what you are describing.  My knowledge of ULP and the data structures, however, is non-existent. 

     

    It appears that the product is not quite ready to do the serious work I was hoping to occasionally do.

     

    You gave me an idea….. What might be an even better workaround might be: for the person that does the teardropsc URL (helpful in preventing breakout with drill wander and providing a more secure connection to vias), to also include an arc (of the same signal) that mostly surrounds the hole, with each end of the arc at the teardrop intersections with the capture pad.  After teardropsc is run as one of the last steps before generating Gerbers, the inner restring value can then be minimized.  The snippet below shows what might result in an inner layer – being just my curved trace, two short traces, and three arcs, to cover the area that needs to be occupied by the normal restring capture pad.  The via hole is the circle in the center.image

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