How does one remove non-functional pads in vias?

what exactly is a: non-functional pads in vias?

I've never heard of such a thing.

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Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Also called a NFP, it is any via capture pad (most often thought of on an inner layer) that does not have an attached trace.  They serve no purpose (see contradictory note) but adversely affect high frequency communications due to their capacitance/inductance, forming an unneeded non-uniformity in the electrical path.  Note: they may serve some purpose if the board gets drilled before lamination, and there is discussion regarding their contribution toward barrel failures one way or the other.  Here are a couple papers and a simple google will yield others:

https://www.altera.com/en_US/pdfs/literature/an/an529.pdf

https://www.speedingedge.com/PDF-Files/anatomy%20of%20a%20plated%20hole.pdf

http://www.circuitinsight.com/programs/53503.html

http://www.ee-training.dk/announcement/high-speed-via.htm

...and many others...

On 12/04/2015 2:33 a.m., Bruce Mellen wrote:

How does one remove non-functional pads in vias?  I’m not finding the

requisite check box(es) or other settings.

I need to minimize the discontinuities in at least the higher frequency

paths, want to somewhat shrink the resulting anti-pads on the ground and

supply layers to improve current return impedance, and it can often

contribute to better routing in the vicinity of vias.

I was hoping to even set it by layer and perhaps set the restring by

layer, having it depend upon whether there is a trace connected or not.

The only alternative seems labor-crazy intensive, effectively:

• Setting normal via restring values and applying the appropriate

teardrops to the various layers

• Minimize the restring values to the smallest NFP values wanted for the

board, and

• apply a circle to each and every capture pad where there is a trace to

be connected

• subsequently approving the circle overlap DRC errors

Please describe a better way…?

 

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So you mean " How does one remove the unused restrings from the inner

layers"

This is all about 'pad stacks' and the ability to specify the restring

by layer or even pad/via. Historically this feature was requested many

times and has not been delivered by Cadsoft. Jorge did mention recently

that they were working on keep-outs for the inner layers so perhaps that

implies pad stacks are coming. As an aside; I note that many of the

power users who were vocal about their need for pad stacks either are

known to have moved away from eagle or are not heard from very often

these days suggesting they have voted with their feet.

You may care to investigate the following ideas:

(1) Edit/delete these unwanted restrings in your Gerber editor.

(2) Don't place the circle, that you subsequently have to approve in the

DRC, on the signal layer but rather on a user defined non signal layers

and merge the signal and non signal layer when you generate the Gerber

for that copper/signal layer.

(3) Create a ULP to automate the 'labor-crazy' part. Again, start as you

have with minimised inner restrings. Use the ULP to locate the inner

restrings that have traces connected. The ULP then adds a polygon

(circle) over that restring of the required size. The polygon is given

the same signal name as the trace so there are no DRC errors.

HTH

Warren

Warren,

Thanks for the potential workarounds; I understand what you are describing.  My knowledge of ULP and the data structures, however, is non-existent. 

It appears that the product is not quite ready to do the serious work I was hoping to occasionally do.

You gave me an idea….. What might be an even better workaround might be: for the person that does the teardropsc URL (helpful in preventing breakout with drill wander and providing a more secure connection to vias), to also include an arc (of the same signal) that mostly surrounds the hole, with each end of the arc at the teardrop intersections with the capture pad.  After teardropsc is run as one of the last steps before generating Gerbers, the inner restring value can then be minimized.  The snippet below shows what might result in an inner layer – being just my curved trace, two short traces, and three arcs, to cover the area that needs to be occupied by the normal restring capture pad.  The via hole is the circle in the center.

On 11.04.2015 16:33, Bruce Mellen wrote:> How does one remove

non-functional pads in vias?  I’m not finding the

> requisite check box(es) or other settings.

This subject is non trivial. Some manufacturers need these rings to

prevent de-lamination of the stack and/or to make a proper via at all.

The ones that don't need it may or may not remove them wihtout asking.

The moral is to always specify what you want with them, wether or not

they are in your gerbers. The specification of the pcb manufacturing is

a process to be taken seriously, especially when you are talking about

high speed signals. Don't go easy on it.

On the other hand, if Eagle supported a way to remove them, it would

direct tell the manufacturer that you don't want them, and allow the

manufacturers DRC to notify if their process doesn't allow.

I'm working on adding an enhancement to the teardrops URL within downloads, to have it to draw connected via capture pads, so if restring is subsequently set to zero, it will effectively remove the non-functional pads.  This will be by layer.  Let me know if any specific feature is desired, or what to watch out for, and I may be able to incorporate.

To your knowledge has this situation changed as far as the toll itself goes?

Did you get anywhere with a viable work around?

Thanks

On 6/15/2017 10:33 AM, Glenn Courtney wrote:

To your knowledge has this situation changed as far as the toll itself goes?

Did you get anywhere with a viable work around?

 

Thanks

 

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Hi Glenn,

I hope you're doing well. The situation has not changed yet, as other on

this thread noted years ago the solution is padstacks which EAGLE does

not yet have.

Now under Autodesk are development resources have increased greatly, so

this is a feature that now has a chance of being developed in a timely

manner. At this time I don't have a timeline for when it will come into

EAGLE.

Sorry I don't have more information for you.

Please let me know if there's anything else I can do for you.

Best Regards,

Jorge Garcia

Autodesk Support

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We have a new forum here <http://forums.autodesk.com>

On 6/15/2017 10:33 AM, Glenn Courtney wrote:

To your knowledge has this situation changed as far as the toll itself goes?

Did you get anywhere with a viable work around?

 

Thanks

 

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To view any images and attachments in this post, visit:

https://www.element14.com/community/message/224125

 

Hi Glenn,

I hope you're doing well. The situation has not changed yet, as other on

this thread noted years ago the solution is padstacks which EAGLE does

not yet have.

Now under Autodesk are development resources have increased greatly, so

this is a feature that now has a chance of being developed in a timely

manner. At this time I don't have a timeline for when it will come into

EAGLE.

Sorry I don't have more information for you.

Please let me know if there's anything else I can do for you.

Best Regards,

Jorge Garcia

Autodesk Support

--

We have a new forum here <http://forums.autodesk.com>