Errors in eagle

Hi,

I think that the red marks that doesn't move are not the 'Print', but they are error reported by DRC... The pad, and all layer move when you move a part. But the errors reported buy ERC will be updated only if you run again ERC.

So before starting to place and route, first try to solve theses errors...

Guillaume.

Ruchi,

I agree with Guillame - what doesn't move are the DRC errors.

You can follow his suggestion and try to solve the errors first.  An

alternative would be to clear the errors with:

    ERRORS CLEAR

on the command line.

With that said, there's a reason why these errors were produced.  Since

none of the related nets have been routed, it's a bit more fundamental.

i.e. the spacing between the FPGA pads is smaller than what is allowed

by the DRC rules.  Take a close look at the tolerances in the DRC - they

may be too tight.  These should be set to the greater of what your board

house can fabricate and your design requirements.

Check all the values in the DRC paying particular attention to the

clearances.

Additionally, it may help to hide the top and bottom stop layers before

running DRC.  I find that the stop mask errors are too numerous to be of

any help and wind up cluttering the significant errors.

HTH,

    - Chuck

On 08/08/2016 07:03 AM, Guillaume barrey wrote:

Hi,

 

I think that the red marks that doesn't move are not the 'Print', but they are error reported by DRC... The pad, and all layer move when you move a part. But the errors reported buy ERC will be updated only if you run again ERC.

So before starting to place and route, first try to solve theses errors...

 

Guillaume.

 

--

To view any images and attachments in this post, visit:

https://www.element14.com/community/message/203353

Ruchi,

I agree with Guillame - what doesn't move are the DRC errors.

You can follow his suggestion and try to solve the errors first.  An

alternative would be to clear the errors with:

    ERRORS CLEAR

on the command line.

With that said, there's a reason why these errors were produced.  Since

none of the related nets have been routed, it's a bit more fundamental.

i.e. the spacing between the FPGA pads is smaller than what is allowed

by the DRC rules.  Take a close look at the tolerances in the DRC - they

may be too tight.  These should be set to the greater of what your board

house can fabricate and your design requirements.

Check all the values in the DRC paying particular attention to the

clearances.

Additionally, it may help to hide the top and bottom stop layers before

running DRC.  I find that the stop mask errors are too numerous to be of

any help and wind up cluttering the significant errors.

HTH,

    - Chuck

On 08/08/2016 07:03 AM, Guillaume barrey wrote:

Hi,

 

I think that the red marks that doesn't move are not the 'Print', but they are error reported by DRC... The pad, and all layer move when you move a part. But the errors reported buy ERC will be updated only if you run again ERC.

So before starting to place and route, first try to solve theses errors...

 

Guillaume.

 

--

To view any images and attachments in this post, visit:

https://www.element14.com/community/message/203353

Hello

Thanks a lot for your advice. What Guillaume said is what exactly i will follow.

The only problem I see is I have like 2000 errors including clearance, dimensions,width, overlap etc.

I am already going crazy with them. The FPGA is a BGA package I do not have much idea of how to handle the spacing in the layout.

I am new to this and its actually very complex.

Best Regards

Ruchi

Hi,

First, you have to  check what the board house can do and can not. Some board house can provide a design rule file for eagle (*.dru), you can sometime found this file on their web site, or you can ask them. If they do, download it, and in the first tab of the DRC window, use the load button to load this file.

If they don't, they surely provide all the data (minimum clearance , width etc..) Some time they provide this information in a document you can download on their website, sometime it's directly on their web site. Anyway you have to adjust all parameters of the DRC with the data provided by the board house.

Often, board house have two or more sets of rules: one set correspond to their standard capability, and of course a standard price. Others sets let you use smaller clearances, width etc... but with an extra cost....

Then you have to look at the components you will use in your design, specially components with small pitch, or special shape. For theses components, you have to carefully look at the dimensions in the recommended layout (sometime it's in the datasheet, sometime you have to found these information on the website of the manufacturer of the component).

The big question here is : 'is the board house capable of doing a PCB with the constraints imposed by the components ?' but you can also ask 'Must I pay extra price to have smaller clearance width etc... ? or standard is enough ?' ... and also 'did I choose the right version of my components ?'  Yeap ! sometime, only one component impose the use of a non standard DRC set, and this component exist in different package : just by choosing the package you can really change the price of your Board !

One solution is put the part in your design an run a DRC. The second solution, is to compare dimension by dimension.

Once you have your answer the problem is easier : you use the right DRC file, compatible with your components

I must admit that at first, this looks terrifying. But you will learn, and you will create your own DRC files. On that part, it's easier if you work with few different board houses: with time you will know their capability.

Just one last thing : I never hesitate to take my phone (or e-mail) to ask to my board house when I have a doubt, or a question :

- It's always a nightmare to realize when the design is complete that it's not feasible !

- A board house what help you on that kind of thing is a better board house that ones what doesn't answer questions !

Guillaume