Polygon problem/bug.

Thanks Warren.

It works when I do it exactly the same way as you describe.

The thing is, apart from a couple of connectors, all components are smd.

So, I prefer to have the outer polygon which usually covers the whole

board,

set to thermals off. Then I want to draw two or three small polygons that

cover

only some throughole connectors with thermals set to on.

This is the opposite of what you proposed and I can't get it to work.

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

Thanks Warren.

It works when I do it exactly the same way as you describe.

The thing is, apart from a couple of connectors, all components are smd.

So, I prefer to have the outer polygon which usually covers the whole

board,

set to thermals off. Then I want to draw two or three small polygons that

cover

only some throughole connectors with thermals set to on.

This is the opposite of what you proposed and I can't get it to work.

--

Web access to CadSoft support forums at www.eaglecentral.ca.  Where the CadSoft EAGLE community meets.

On 7/10/2016 10:34 p.m., Joop wrote:

Thanks Warren.

 

It works when I do it exactly the same way as you describe.

 

The thing is, apart from a couple of connectors, all components are smd.

So, I prefer to have the outer polygon which usually covers the whole

board,

set to thermals off. Then I want to draw two or three small polygons that

cover

only some throughole connectors with thermals set to on.

This is the opposite of what you proposed and I can't get it to work.

 

Hi

There is a way to do it. See the attached

The board sized outer GND polygon is made Rank 3, Thermals 'Off'.

That makes the whole board, Thermals off and satisfies your SMDs.

Next you thwart its efforts in the region of you connector with a

polygon at Rank 2 with an Eagle generated signal name like S$7.

Rank 2 is a higher ranking than the big polygon so the big polygon

cannot go into that area. Hence there's a hole in the big polygon in the

region of your connector.

The you make another polygon a little larger than the last and give it

Signal = GND,  Rank 1 , Thermals 'On'.

Having a higher rank it wins and  suppresses the rank 2 polygon

underneath it so the Rank 2 polygon becomes irrelevant but it's still

doing its job holding the big rank 3 polygon at bay.

With the RAnk1 polygon having  Thermals 'On', the connector pads have

thermals as desired.

Now there is an issue to be understood.

Do a ratsnest and look in the spaces beside the traces. There's

something there. It's the drawn outline of the unfilled Rank 2 polygon.

This is a visual effect only in the CAD display.

When you create your Gerber files, it is not there because the drawn

polygon outline is not part of a Gerber. It is the calculated signal

polygon that is conveyed to the Gerber.

View the gerber to confirm this for yourself.

I suspect, any print output from Eagle used to home-bake a board may

show these display artefacts.  I did not check this.

I understand many create the gerber and print that for their toner

transfer or photo process.

HTH

Warren