ULP: write CSV file with net information

Hello,

Warren has made a good suggestion, to give you a complete netlist of your design. If you need to go further than this to determine source/target of every net then it's an interesting idea, although to do what you are trying to do isn't perhaps as simple as it sounds.

Firstly, you'll need to ensure that all your components have their pin types set correctly (a lot of 3rd party libraries wont have this information correctly configured) which is fine if you are creating all your own libraries (which you definitely should). Then you'll need to examine the pin type of each node connecting to a net to find the source, which is fine if there are obvious output and input pins but what if you have bidirectional pins? You'll need to have some way to determine what you need in this case.

Secondly, when you've determined the source, that's fine for simple 1-to-1 connections, or even 1-to-many, but what happens when there are passives components which form part of an overall path? You'll need to then note which end of those is the target to another source so you can work out that their other end is a source to go to other targets. It's all doable I think, just not simple, and would likely require a lot of user input to make decisions on resolving unknowns.

Could you expand on the reason you are trying to do this? It might help us find another existing way to achieve your goal.

Best Regards,

Rachael

Hello,

Warren has made a good suggestion, to give you a complete netlist of your design. If you need to go further than this to determine source/target of every net then it's an interesting idea, although to do what you are trying to do isn't perhaps as simple as it sounds.

Firstly, you'll need to ensure that all your components have their pin types set correctly (a lot of 3rd party libraries wont have this information correctly configured) which is fine if you are creating all your own libraries (which you definitely should). Then you'll need to examine the pin type of each node connecting to a net to find the source, which is fine if there are obvious output and input pins but what if you have bidirectional pins? You'll need to have some way to determine what you need in this case.

Secondly, when you've determined the source, that's fine for simple 1-to-1 connections, or even 1-to-many, but what happens when there are passives components which form part of an overall path? You'll need to then note which end of those is the target to another source so you can work out that their other end is a source to go to other targets. It's all doable I think, just not simple, and would likely require a lot of user input to make decisions on resolving unknowns.

Could you expand on the reason you are trying to do this? It might help us find another existing way to achieve your goal.

Best Regards,

Rachael

Hello Rachael,

thank you!

I use Eagle not for electronic parts. I draw audio/video/multimedia components and their connections. I also print the labels for this parts (Matrix, Loudspeaker, Amplifier, HDMI Extender, ...) with ulp export

I draw each pyhsical component (Beamer, Loudspeaker, Matrix, ...) with their inputs and outputs.

Normaly I have only 1-to-1 connections, like:

Ethernet

RS232

RS485

Loudspeaker cable

HDMI cable

...

So 1-to-many I don´t use.

For me, a net ist as example a HDMI cable ... this has a one start point and one end point.

So each net has:

start point (source) --------- net name ------------ end point (destination)

I set up each pin:

in

out

io

pwr

I loop now over all nets and for each net I loop again over all nets:

In the second loop I check for:

If same netname

If source pin is IO or OUT

If part name is not equal (because to remove dulpicates)

SCH.sheets(SH)

{

SH.nets(N)

{

N.segments(SEG)

{

SEG.pinrefs(P)

{

cablename = N.name;

SH.nets(N1)

{

N1.segments(SEG1)

{

SEG1.pinrefs(P1)

{

if(N.name == N1.name && (P.pin.direction == PIN_DIRECTION_OUT || P.pin.direction == PIN_DIRECTION_IO) && (P.part.name != P1.part.name)){

from = P.part.name + " (" + P.part.value + ")";

to = P1.part.name + " (" + P1.part.value + ")";

cabletyp = N.class.name;

This works in the first version :-)

Hans König wrote:

 

I use Eagle not for electronic parts. I draw audio/video/multimedia components and their connections. I also print the labels for this parts (Matrix, Loudspeaker, Amplifier, HDMI Extender, ...) with ulp export

 

I draw each pyhsical component (Beamer, Loudspeaker, Matrix, ...) with their inputs and outputs.

Normaly I have only 1-to-1 connections, like:

Ethernet

RS232

RS485

Loudspeaker cable

HDMI cable

...

 

So 1-to-many I don´t use.

 

For me, a net ist as example a HDMI cable ... this has a one start point and one end point.

 

So each net has:

start point (source) --------- net name ------------ end point (destination)

I see now, that's a cool alternative use for EAGLE, I like it

Hans König wrote:

 

I set up each pin:

in

out

io

pwr

 

 

I loop now over all nets and for each net I loop again over all nets:

In the second loop I check for:

If same netname

If source pin is IO or OUT

If part name is not equal (because to remove dulpicates)

 

SCH.sheets(SH)

{

SH.nets(N)

{

N.segments(SEG)

{

SEG.pinrefs(P)

{

cablename = N.name;

SH.nets(N1)

{

N1.segments(SEG1)

{

SEG1.pinrefs(P1)

{

if(N.name == N1.name && (P.pin.direction == PIN_DIRECTION_OUT || P.pin.direction == PIN_DIRECTION_IO) && (P.part.name != P1.part.name)){

 

 

from = P.part.name + " (" + P.part.value + ")";

to = P1.part.name + " (" + P1.part.value + ")";

cabletyp = N.class.name;

 

This works in the first version

Excellent, I'm glad you managed to get it working

If you need any more help just ask, but it seems like you have this well in hand now.

Best Regards,

Rachael