unpopulated 4 layer board came back shorted between 3v3 and gnd. Cannot find the issue

If you have access to a themal camera, you can put a power supply that has  current control on the two lines.

Either the heat will show up on the camera and indicate where the short is, or the current will burn away the short. A win in both cases.

I kind of started cleaning up the board in general (still wanting to try to solve/understand the issue I'm facing). So if the boardhouse says clearance is 5mil. Changing to 6 mil wouldn't heart as a start.
Read about hairline short circuit and so on and realize I might be oversimplifying the PCB layout magic. Trying to go from white-belt to black-belt without passing a few colors along the way.
Have a USB diff pair that I didn't meander to matched lengths and so on. I will be ordering another itteration of my board but was hoping to get it off the ground at least. But VCC->GND short ruled that out...

My board routed to 98% using the autorouter but this version is me trying to manual route it. If I define nets and setup clearances with a bit of wiggleroom does the autorouter really work or is it always better to route manually?

Meandring USB signals are advanced topics. Maybe focus on all the basic layout priciples first? Get that USB ones as close to the edge as possible and forget about them. Focus on all those other components.

Hi

I think you have design rules problems.

You've set the via from L1 to L16 but your power 3V3 goes to L2. That causes an overlap on this pin.

Here you either have to put the Via only between L1 and L2 - Layer Settings, or a blocking area on the L16 make sure that the GND area (polygon) does not short here.

Then you have approved a lot of mistakes that are not! may be approved.

They are e.g. air wires, wire stubs, restricts, distances, clearance

Wire stubs can be approved if they are not too close to the neighboring tracks.

Also check the part names and labels especially on the holes and components.

You can adjust the font sizes and styles to avoid overlapping the holes.

This was a first check. Please make the ERC and the DRC so often that it fits and no approval is needed.

Graphical details in the part borders can be switched off, but it is worthwhile if these are also checked.

You can set this in the design rules, or activate in the menus.

Best Regards

Gerald

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Hi

I think you have design rules problems.

You've set the via from L1 to L16 but your power 3V3 goes to L2. That causes an overlap on this pin.

Here you either have to put the Via only between L1 and L2 - Layer Settings, or a blocking area on the L16 make sure that the GND area (polygon) does not short here.

Then you have approved a lot of mistakes that are not! may be approved.

They are e.g. air wires, wire stubs, restricts, distances, clearance

Wire stubs can be approved if they are not too close to the neighboring tracks.

Also check the part names and labels especially on the holes and components.

You can adjust the font sizes and styles to avoid overlapping the holes.

This was a first check. Please make the ERC and the DRC so often that it fits and no approval is needed.

Graphical details in the part borders can be switched off, but it is worthwhile if these are also checked.

You can set this in the design rules, or activate in the menus.

Best Regards

Gerald

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Seriuosly Awesome Gerald!!!

I mean could I send you a gift I would!
I know there where a lot of DRC findings on the board.
Airwires:
I was too lazy here for sure, If I find these really short airwires I just confirm the routed line is on the pad (I.e copper i solid)
Must be something in the way I work with Eagle that leave this small gaps. I think Its related to how I place the (micro)vias in pads.
I have done two layer boards for a year of so and for me plating (tenting the via?) is not an issue. I do know these holes will suck down solder.
And a few of my smaller components on this board has thermalpads where these 4-5 microvias actually make up a significant area of the pad.
I try to fill them my self prior to applying solder via stencils. These are one-off's so I assemble the board manually. For production runs I would either not place them in pads or go for more expensive manufacturing where vias are tented(plated)

Clearances:

I'd like to think I addressed all clearances not related to vias in pads. But CLEARLY you found one I must have "passed" in a hurry. Will never do that again!

Restricts:There is a ESP32 with onboard antenna therefor having the restrict on the toppart of the board. I have a few components that simply have to be there. Tried to avoid that area to my best abillity.
This will affect the signal reach for sure. But ok.

About DRC/ERC rules. They are all coming from OSHPark and I just come to realize maybe only to use them as guides and maybe nudge here and there (upwards).
Maybe have an OSHPark-lay-original and a OSHPark-4lay-safe file.

OSHPark does not allow for any other than drilling through layer 1-16. No blind or burried vias so I probably wont be doing these types of board anytime soon. Simply too expensive for iterative oneoff's on a budget :-)

I will un-clear all my errors and pass them with more care this time. I think I would have miss that 3v3 drill straight into the thermal :-)

Thanks Gerard!!!