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Autodesk EAGLE
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Autodesk EAGLE
Forum First advanced EAGLE design, having various issues
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Related

First advanced EAGLE design, having various issues

Former Member
Former Member over 14 years ago

THIS ISSUE IS FIXED, SEE FURTHER DOWN FOR NEXT PROBLEM

I'm designing a circular board with a BGA and lots of different IC's on it and I'm having various problems. I'll start with my first one, regarding Blind Via Ratio error in DRC:

 

Layers setup in DRC:

image

Sizes setup in DRC:

image

 

I end up with these warnings everywhere:

image

 

I have a number of other issues, but I thought I'd take them one at a time. Any help is very much appreciated!

 

Regards,

Peter Hygren

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  • Former Member
    Former Member over 14 years ago

    Hi Peter,

     

    In your case, i think that the best thing to do is to ask Richard Hammerl, who is the expert of cadsoft.

    link

     

    Best regards

     

    Nicolas

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  • Richard_H
    Richard_H over 14 years ago

    Hi Peter,

     

    the problem seems to be in the settings for Sizes in the Design Rules. You have 0.5mm for micro vias and for 'normal' vias. This does not allow EAGLE to dinstinguish between them and I suppose this is the reason for the errors. Usually the value for normal vias is higher than for micro vias. As far as I can see it from your Desing Rule settings, I think you don't use real micro vias. What happens if you decrease the micro vias value?

     

    Regards,

    Richard

     

    For further evaluation it would be good to send me your board file by email.

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  • Former Member
    Former Member over 14 years ago in reply to Richard_H

    I changed my layer settings to only have one via type and the problem went away, on to a much more urgent problem:

     

    I have a supply layer (GND) that doesn't behave like it should regarding clearing room for vias and THT pins:

    (brown is GND plane obviously)
    image

    My layers:

    image

    And the GND layer:

    image

    The fill layer does however treat ground pins/vias correctly:

    image

    I need help urgently to solve this matter, any help is deeply appreciated. I'll send brd file on request via mail.

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  • Former Member
    Former Member over 14 years ago in reply to Former Member

    BUMP

    Hasn't anyone else run into this problem?

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  • Richard_H
    Richard_H over 14 years ago in reply to Former Member

    You defined a supply layer which is displayed inverted and has its own anullus and thermal symbols. This is reflected by the $ character in the beginning of the layer name.

    May be I may add some text from the FAQs:  http://www.cadsoft.de/faq.htm

     

    Supply Layers, Power Planes, Polygons in Inner Layers - What is what?

     

     

    If you would like to use copper planes in inner layers you should be aware of several things and know  how this works:
    EAGLE uses so-called Supply layers, that will be generated automatically and lead one single signal. And there are the quite "normal" inner layers that use polygons for copper planes.
    EAGLE considers its Supply layers as a special kind of inner layer.

    Supply Layer:
    This one can be activated with the Supply option in the DISPLAY menu, Change button. The layer name determins the signal that will be lead in this layer:
    If you use, for example, the name GND, and activate the Supply option, the resulting layer name is $GND. The $ character is the identifying mark for a Supply layer. This can be done also with the help  of the LAYER command, for example: LAYER 3 $GND
    Specials of a Supply layer
    a) The layer is displayed inverted, i. e. everything drawn in this layer is non-copper on  the real board.
    b) This layer does not work with Pads and Vias. Connected elements will automatically get Thermal symbols if required, isolated elements will get isolating rings, so-called Annulus symbols. The dimensions of these symbols can be adjusted in the Design Rules' Supply tab.
    c) To keep the board edges free of copper draw an isolating WIRE near the border. This avoids  possible short circuits between adjacent (Supply) layers.
    d) It is not possible to draw traces in a Supply layer (inverted display!).
    e) For manufacturing data generation (for example Gerber) with the CAM Processor you have to activate the Supply layer only, nothing else! No Vias, no Pads!
    f) And again: The layers Pads and Vias have nothing to do with the Supply layer. To see what's the matter in this layer you have to display only this Supply layer. And remember the inverted display.

    Inner Layer with copper planes - the "normal" power layer:
    In this case the inner layer will be treated the same as the Top or Bottom layer. Pads and Vias are necessary for connecting the polygons. The width of the polygon also determins the width of the traces that connect Pads or possibly Vias in Thermal symbols. Polygons follow the given Clearance values of the Design Rules.
    What do we have to keep in mind?
    a) Pads and Vias in inner layers are basically of round shape and are usually smaller in diameter than they are in Top or Bottom layer (see Restring settings in the Design Rules). With the default  setting in EAGLE (layer color for Pads and Vias is green) the differences in shape and diameter are not visible in the Layout Editor. If the inner layer is displayed with Pads and Vias, it might happen that the distances seems to be too close. But this is not the case!
    Here is makes sense to change the layer color for Pads and Vias to the background color (DISPLAY, Change, Color). Now Pads and Vias are shown with the respective color of the currently active signal layer(s). It is possible to distinguish different shapes and diameters of each signal layer.
    b) Do you want to place several signal planes in a common layer? Then you may use several polygons with different names. Here it makes sense to use them with different Ranks.
    c) You are allowed to draw additional traces. The polygons keep their respective clearances. Keep an eye on the copper areas. It might happen that they will be devided into pieces and that there will appear airwires that represent not connected elements. RATSNEST should report Nothing to do! when the design is finished.

     

     

    HTH Richard

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  • Former Member
    Former Member over 14 years ago in reply to Richard_H

    Thank you Richard, that explains everything!

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