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  • Author Author: shabaz
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Scrutinize my FPGA PCB Layout

shabaz


Since  alerted everyone to the PCB Forum, I thought I’d make use of it and try to get some help.

I’ve never done a ball grid array (BGA) layout, and I wished to have an FPGA board that I’d created myself, for some experimentation and general FPGA learning.

I’m planning to create a board using a Lattice Semiconductor part, because it is available in a sensible TQFP package which I am comfortable with. However, I thought I’d also give a Xilinx part a shot too, but it’s only offered in physically smaller packages; the simplest of which is what Xilinx calls an FTGB196 package. The part I’m using is Xilinx XC7S15 (PDF data sheet overview). However, since I've started the design, the chip is unobtainable! nevertheless, I thought it would be still useful to continue the design, and build it when the parts become available again.

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The balls are spaced 1.0 mm apart, so it’s perhaps as friendly as such a type of package can get, I guess. I wish to use this with a 4-layer board, using low-cost PCB services from China.

I’ve gone with the following pad dimensions:

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Here is each layer of the board, in the FPGA region.

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This is what the board currently looks like zoomed-out(ground plane not shown), everything is still in the process of being routed, but basically I’m using layer 2 for ground plane, and layer 3 has some power planes.

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Top and bottom layers (red and blue respectively) are for signal traces, and for all DC-DC converter traces, so I’ll use lots of vias when I pass the power to the power plane layer.

This is what the traces look like underneath the FPGA:

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I need three supply voltages, and I’ve routed the DC-DC converter sections as visible in the screenshot above, but they still need to be positioned better. There is a basic power sequencing IC, not laid out on the PCB yet, it is LM3881, which too is now hard to obtain, but I have a few for now. Perhaps I can swap that out to a microcontroller if the LM3881 is inadequate, but it seemed fine. There's no JTAG programmer on-board; instead there will be a socket for the Xilinx programmer, just to keep things fairly minimal currently.

For additional memory, the FPGA is connected to a RAM chip (SRAM) on the right side. This is easier than DRAM. It’s messily routed currently.

I still need to route most of the signals in the IO banks; all that is done is the supplies, and the IO used for the SRAM.

Schematic

The schematics are incomplete, I still need to add connectors for the I/O. The project will be ported to KiCAD ideally (I started in EAGLE, but now I believe I can import it into KiCAD 6). The three sheets are shown below.

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Anyway, that’s as far as I have got. Feel free to discuss/criticize etc : ) I’ll try to take on board any comments, however, I don’t want to re-do too much of it unless there’s a functional risk of it not working – for instance, some of the design admittedly looks anachronistic, like the massive DC-DC converters, and relatively physically large SRAM chip, but I really didn’t want to use tiny package devices except where I have no choice, i.e. the FPGA. I’d rather make the rest of it as large and serviceable as possible.

Thanks for reading!

  • in reply to wolfgangfriedrich

    Hi Wolfgang,

    Thank you for these tips! The trace width values you provide are very helpful, I will thicken the power/ground traces. I can't recall why I went with 4mil instead of 5 mil for the signals underneath the FPGA, I may have hit some DRC limit based on the low-cost factory capability specifications, but I started the board so long ago, I'll need to re-check. Hopefully I can thicken that up to 5 mil too.

    The circles/horizontal lines are a documentation layer, they were a reminder to treat those pads differently while routing (I think they are unused, and have no pad escaping - or some other reason, I'll have to recall!). Similarly I will delete the escape vias for other pins too, once I have started routing the remainder I/O, and discovering which ones I cannot easily route, and eliminating those. I don't have the experience to do that without this trial-and-error routing attempt first :( This will be a basic experimentation board, so I don't need to route all I/O as you say, and can simplify things.

    I believe I created some simple VHDL to connect to SRAM, to see which I/O Vivado preferred, and then played with moving some around in the pin assignment file to see if Vivado was still ok with them, because I currently have no instinct how good the routing capability is inside their software (I'm an FPGA beginner).  I need to re-install Vivado to confirm that. Also, I'd have to check, but since it's SRAM, I think I can freely swap around address/data lines, there may be some optimal wiring configurations, I'll examine the SRAM datasheet.

    The SRAM is 3.3V, and good point on the termination resistor(s). I'll see what I can do! I have 4-packs of 33 ohm resistors, which are reasonably small but hand-solderable so they could be used. It will be great to have good performance there since it's capable of 10 nsec access time.

    The unusual angles there are temporary, I take two attempts at routing, the first is topological, and then I rip up the traces on-by-one for the second attempt. Agree on the regulator positioning, they are badly placed at the moment.

    That's awesome that you don't mind looking at the schematic too! I'll add that to the blog post now, so that it doesn't get buried in the comments. Thanks again!!

  • in reply to jc2048

    Hi Jon,

    These are great points. I too do the same thing, filling that third layer with ground where no other planes are necessary. Decoupling capacitors do a better job there than any capacitance across the large board distance between those layers, but still, it's easier to route power signals as a single polygon if it's concentrated in one area.

    Here's an example where only three layers are used (layer 1 for signals, layer 2 for ground plane, and layer 3 for power plane only where it was needed, there was no significant benefit in extending it), and it was unnecessary to have a 4th layer because there were no signals on the bottom layer. Some would argue this could have been a 2-layer board, but it's an easier transmission line at the desired impedance with 4-layer due to the distance between the top two layers. This board operated from tens of MHz to close to 2 GHz.

    image

  • Some comments and questions:

    - A good rule of thumb is that traces into BGA pads can use up to 25% of the circumference of the pad. With a 0.4mm pad you can use 0.3mm (12mil) width for the power and gnd traces. And 0.127mm (5mil) signal traces might help with pricing at the budget board houses as well.
    - Pad layout looks good in general, vias under the BGA shall be tented with soldermask to avoid shorting to neighboring balls. What are the 7 pads of the FPGA with white circles around them and the 4 horizontal lines? If they are silkscreen, they should be removed.
    - Any BGA IO pin that is not used should not have a fan-out trace and via. Un-needed holes in the planes on layout 2 and 3 can be avoided that way.
    - I did not check the Xilinx part for a dedicated SRAM interface, but assuming you are just using GPIOs of the FPGA for the SRAM interface you could align them much better to the SRAM pins. Having trace from the top row of the SRAM going to the bottom half of the BGA are more difficult to route, than having as many traces as possible running horizontally and then to a close IO pin. Cross-talk is not a major concern with a reference plane underneath.
    - For power supply integrity it is better to have one ground plane and one power plane going all the way between the IO banks of the FPGA and the memory chip. Every time signals cross from top to bottom, as decoupling cap should stitch power and GND together, so it is useful to group signals that cross sides together. Is the SRAM 3.3V or 1.8V?
    - At least the clock signal to the SRAM should have a series termination resistor. Ideally all signals should be terminated if EMC is a requirement. There are 4-packs of resistors in small packages. Moving the SRAM further away and lengthen the traces is a trade-off well worth for this. The resistor packs are ugly to hand-solder though.
    - Soldering the board by hand seems doable with either a reflow oven or hot plate and a decent temp profile. If you decide to have the board assembled by a company, add two local fiducials at 2 opposite sides of the FPGA, the pick&place with thank you :).
    - Shall we start a flame-war about odd angle traces ;)

    - Review of the schematic in context to the layout might add some more insights, if you are willing to share it. 

    - Moving the 1.0V regulator to the 10 o'clock position around the FPGA seems to lead to a more efficient power flow.

  • in reply to neuromodulator

    That's a great video, thanks for the link! I've only watched about 40% of it so far (at 1.5 times speed works well) and it is extremely helpful. 

    There's recently been some videos on the topic of how signals travel where really long wires/traces are involved, there's a long thread on eevblog and I have not participated because some super-competent people are doing a great but very uphill job there however there is a lot of stubbornness/sustained misconceptions from others which is a shame because it makes it super-hard to learn from the thread for newcomers I expect.  Still, it's been quite an eye-opener reading that thread, how many people believe that the energy would take ages to arrive because of a refusal to believe even when explained, that the two wires possess characteristics that would (near-) instantaneously pass current and energy, and, (at high-level first approximation anyway, without being pedantic about wire resistance for example) continue to do so, indefinitely if the wire pair (or wire with ground plane underneath, or coax of course) is of infinite length.