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  • Author Author: shabaz
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Scrutinize my FPGA PCB Layout

shabaz


Since  alerted everyone to the PCB Forum, I thought I’d make use of it and try to get some help.

I’ve never done a ball grid array (BGA) layout, and I wished to have an FPGA board that I’d created myself, for some experimentation and general FPGA learning.

I’m planning to create a board using a Lattice Semiconductor part, because it is available in a sensible TQFP package which I am comfortable with. However, I thought I’d also give a Xilinx part a shot too, but it’s only offered in physically smaller packages; the simplest of which is what Xilinx calls an FTGB196 package. The part I’m using is Xilinx XC7S15 (PDF data sheet overview). However, since I've started the design, the chip is unobtainable! nevertheless, I thought it would be still useful to continue the design, and build it when the parts become available again.

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The balls are spaced 1.0 mm apart, so it’s perhaps as friendly as such a type of package can get, I guess. I wish to use this with a 4-layer board, using low-cost PCB services from China.

I’ve gone with the following pad dimensions:

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Here is each layer of the board, in the FPGA region.

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This is what the board currently looks like zoomed-out(ground plane not shown), everything is still in the process of being routed, but basically I’m using layer 2 for ground plane, and layer 3 has some power planes.

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Top and bottom layers (red and blue respectively) are for signal traces, and for all DC-DC converter traces, so I’ll use lots of vias when I pass the power to the power plane layer.

This is what the traces look like underneath the FPGA:

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I need three supply voltages, and I’ve routed the DC-DC converter sections as visible in the screenshot above, but they still need to be positioned better. There is a basic power sequencing IC, not laid out on the PCB yet, it is LM3881, which too is now hard to obtain, but I have a few for now. Perhaps I can swap that out to a microcontroller if the LM3881 is inadequate, but it seemed fine. There's no JTAG programmer on-board; instead there will be a socket for the Xilinx programmer, just to keep things fairly minimal currently.

For additional memory, the FPGA is connected to a RAM chip (SRAM) on the right side. This is easier than DRAM. It’s messily routed currently.

I still need to route most of the signals in the IO banks; all that is done is the supplies, and the IO used for the SRAM.

Schematic

The schematics are incomplete, I still need to add connectors for the I/O. The project will be ported to KiCAD ideally (I started in EAGLE, but now I believe I can import it into KiCAD 6). The three sheets are shown below.

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Anyway, that’s as far as I have got. Feel free to discuss/criticize etc : ) I’ll try to take on board any comments, however, I don’t want to re-do too much of it unless there’s a functional risk of it not working – for instance, some of the design admittedly looks anachronistic, like the massive DC-DC converters, and relatively physically large SRAM chip, but I really didn’t want to use tiny package devices except where I have no choice, i.e. the FPGA. I’d rather make the rest of it as large and serviceable as possible.

Thanks for reading!

  • in reply to Andrew J

    Hi Andrew,

    I'm glad you're mentioning it, because it's a very good point (it's effectively transmission lines that are carrying the signals, and that is a non-intuitive topic, that I believe is only really come across either briefly at uni-level, or far more likely through later self-study or practical projects and on-the-job experience). 

  • in reply to shabaz

    ‘Those signals are going to have a return path that follows the trace so you’ll need to be careful with the ground plane by those traces, with vias to the ground plane by the trace.”

    I realise I wasn’t very clear with this point.  Where a high frequency signal trace vias between layers you also want a ground plane via as close as possible so the return doesn’t have to wander off looking for a path when it’s inclination is to follow the signal trace.  By the same token, don’t have your high frequency signal traces cross a gap in the ground plane: thst is surprisingly easy to forget about.  I feel like I’m teaching you to suck eggs here, sorry, but maybe other readers will benefit.

  • in reply to cstanton

    For a 4-layer board like this, I'd have used the two inners as planes, with layer 2 as the ground and layer 3 as the power. I suppose that was just 'convention', though there may be an argument for having the ground more 'solid' than the power (there's a small amount of inductance to the vias, so there may be a small advantage to minimizing the distance from the ground plane to the component ground power pads, assuming the components are mostly on layer 1). It possibly also helps where you have sensitive areas around a chip, like those relating to pll filters caps, and that kind of thing. Another benefit might be with parts that have ground pads underneath the package for heatsinking. The board material - fibreglass and resin - is a good insulator, so you depend on the vias to carry much of the heat flow. If you only neeed to carry down about 0.2mm to layer two before the heat can spread sideways on the plane (that's with the typical, traditional impedance-controlled stackup that gives 6 thou tracks for 50R), that has to be better than carrying the heat down ~1.2mm down to layer 3.

    With high-speed logic, for good signal integrity, the traces really do need to 'work against' continuous planes (as mentioned by Andrew, elsewhere in the comments) and you need to consider the decoupling between planes with that in mind, not just the more obvious requirements of the power distribution. Having the plane continuous underneath generally applies to differential pairs as well, even though, at first thought, you might consider that, as the return current runs in the other half of the pair, a board plane return is unnecessary (normally, dimensions dictate that the pair has to be arranged so that the plane is acting as a capacitively coupled intermediary between the two traces, and currents need to run underneath the tracks, even if they're only circulating round and round and don't end up flowing anywhere else).

  • I haven't tried a design around of ICs of the complexity of the ones that you want to use, but I found 2 sources that give some pretty good advice on how to design these kind of PCBs. One is a video of Rick Hartley about grounding (www.youtube.com/watch, were he discusses all about different stackups. One thing he shows in that video is that referencing signals to a power plane is not that good (i.e referencing to ground is much better). Of course in the end it all depends on each case, and there are going to be always tradeoffs, or time where you will have to break the best practices. One nice blog where the author explores designs that are less than ideal is a blog by Jay Carlson (https://jaycarlson.net/embedded-linux/). There he shows a couple of interesting things:
    - It is possible to solder 0.65 pitch at home with a hot-plate.
    - 4 layers is enough to get relatively complex BGAs to work (although they may not be EMC ideal)
    - Memory track-length matching is much more forgiving than what manufacturers recommend.

  • in reply to cstanton

    If design allows it, I put the ground/power layers in the middle, and the business traces on the outsides. That allows access to those traces, and I may be able to correct small mistakes made in the routing. If a trace is in the middle of the board, you can not cut it with a knife if misrouted.