Role for FPGA or CPLD with Raspberry Pi

On DesignSpark:

• TAUTIC - CPLD Development Board Review
• http://www.designspark.com/content/tautic-cpld-development-board-review

The red board connected to the black CPLD header is the Bus Pirate he mentions.  I've got one of those, and they're very handy little gadgets.

At that CPLD size, I'd just go with a Xilinx XC9572XL-10TQ100CXC9572XL-10TQ100C in a 44-pin PLCC, which plugs into a PLCC socket, which in turn plugs into a wire-wrap socket or socket strips.  For some reason, I've often found 72 macro-cells to be just enough and 64 macro-cells to be "not quite enough".  XC9500XL are even older than Coolrunner-II, but they're still listed on the top CPLD page at Xilinx.com.

Edit: it seems someone changed my reference to the 9572XL into a full part number including -10TQ100C.  I don't mind, except that the TQ100C is the 100-pin TQFP package.  If you want to wire-wap, you'll need the 44-pin PLCC version which is XC9572XL-10PCG44C.

Good to know that's available in PLCC, thanks.

It's been a long time since I heard anyone mention wire-wrap though.   I have a huge collection of wire-wrap tools and wire and sockets packed away in a trunk somewhere, probably never to be used again. Those were the days ... not necessarily good, but easy.

Just came across this Kickstarter created for digital logic education and it looks to be using that chip:

The Binary explORer boArd (BORA)

http://www.kickstarter.com/projects/545073874/bora-the-binary-explorer-board

In many ways this board looks like quite a good idea but it's totally let down by using an ancient CPLD, the XIlinx XC9572XL-10TQ100CXC9572XL-10TQ100C. Xilinx just don't do CPLDs any more - they go on making some of the old stuff but there's been no effort put in for years.

On the other hand there is good new stuff from Lattice which seems to get ignored by the bulk of engineers who look no further than A or X.

The great thing about using  a modern CPLD is that you can keep it simple if you like and do a few gates in block diagram, Verilog or VHDL but if you want you can embedd a whole processor as well.

I think RPi FPGA needs something better than the XC9572XL-10TQ100CXC9572XL-10TQ100C.

Michael Kellett

Michael Kellett wrote:

 

In many ways this board looks like quite a good idea but it's totally let down by using an ancient CPLD, the XIlinx XC9572XL-10TQ100CXC9572XL-10TQ100C. Xilinx just don't do CPLDs any more - they go on making some of the old stuff but there's been no effort put in for years.

 

On the other hand there is good new stuff from Lattice which seems to get ignored by the bulk of engineers who look no further than A or X.

 

The great thing about using  a modern CPLD is that you can keep it simple if you like and do a few gates in block diagram, Verilog or VHDL but if you want you can embedd a whole processor as well.

 

I think RPi FPGA needs something better than the XC9572XL-10TQ100CXC9572XL-10TQ100C.

My opinion: for the purposes of teaching the fundamentals of digital logic, the XC9572XL-10TQ100CXC9572XL-10TQ100C is a great part.  You can do a lot with those 72 macrocells, well beyond what is needed in a first course on logic.  Xilinx still makes the XC9572XL-10TQ100CXC9572XL-10TQ100C because they still sell -- it's a great way to get a modest amount of instant-on reasonably high-performance logic for about US$1.  With more than 72 macrocells, you probably want an FPGA rather than a CPLD.  I don't see Xilinx as having given up on CPLDs -- I think it's more of an "if it ain't broke, don't fix it" situation.

My decades-old programmable logic bugbear is that the internal architecture is hidden, so you have to use an x86 PC to run the design tools.  Yes, I realize that Xilinx tools run on GNU/Linux and they're free-as-in-beer, but it means that there are no open-source tools so you can't run the design tools on (for example) a RasPi and get a nice self-contained educational package for under US$150 (RasPi + Motorola LapDock + FPGA/CPLD board).  You need to have an x86 PC nearby and run the design tools on it, in which case why bother with the RasPi at all?  Plus the Xilinx tools are IMO complex to use and understand, adding a layer of difficulty to the educational mission.

So here's my question: is the binary format for the XC9572XL-10TQ100CXC9572XL-10TQ100C open or publicly reverse-engineered?  If it is, you get the advantage of doing the logic minimization with open source code and downloading the resulting binary directly from RasPi GPIO.  If the binary format isn't open, the board might as well have a modest FPGA (e.g., Xilinx XC3S50A) or just buy a Lattice iCEblink40 while they're still US$19.

Excellent subject, interesting for education and enthusiasts alike.

So here's a question --- what is the most complex programmable logic device (in the most generic sense of the phrase but not including CPUs) on the market today (old is OK as long as the device is still sold) that can be fully examined and programmed with open source EDA tools?  Since no modern CPLDs let alone FPGAs are open enough for that, what's the best that can be done?

Addendum: The reason for the question is the unfortunate state of affairs outlined by John, which prevents a cheap ARM system from being used as a complete and standalone EDA platform for introductory EE education in programmable logic.  But if we reduced our expectations in terms of modernity and size of programmable logic devices that can be handled, perhaps there is still some milage available there?  Certainly a standalone Pi or other cheap ARM board dedicated to such a function would be a wonderful asset in the FOSS arsenal even if severely limited in device capability.

Morgaine Dinova wrote:

 

So here's a question --- what is the most complex programmable logic device (in the most generic sense of the phrase but not including CPUs) on the market today (old is OK as long as the device is still sold) that can be fully examined and programmed with open source EDA tools?  Since no modern CPLDs let alone FPGAs are open enough for that, what's the best that can be done?

I had high hopes for the Cypress PSoC5 when I first heard about it, especially after I heard the highly-spirited  Cypress CEO T.J. Rogers talk about at the 2009 ARM conference.  The PSoC5 has a bunch of digital blocks, each of which can have two "12C4" PLDs.  I got discouraged when I found out that they didn't provide enough information in the tech refs to program the routing matrix, insisting I use their proprietary tools.  Perhaps this has changed with newer tech ref editions -- I haven't checked lately.  I always ask about this when I get an opportunity.  It could be a pretty nifty platform for digitial exploration if you could get at all the architectually-defined features.

One thing I particularly liked in Dr. Roger's 2009 presentation was when he mentioned that the basic FPGA patents held jealously by Xilinx and Altera were about to expire, leaving the field wide open to futher innovation.  So who knows?  T.J. is notoriously unpredicatable.

In terms of what can be done right now, there's always Wheeler's Law: ""All problems in computer science can be solved by another level of indirection".  It's an awful way to do it, but you could take a large FPGA and dedicate 80-90% of its LUTs* to form a routing matrix implemented as an array of multiplexers implemented using distributed RAM cells.  The remaining LUTs would be RAMs for implementing n-input logic functions.  I believe you can update the contents of distributed RAM cells over JTAG using Xilinx documentation, so you can update both the logic function and the routing.  Since all routing would be through RAM cells instead of pass transistors, it would be way slower than using an FPGA properly, but as a teaching tool it's "something that can be done now".

I think I heard of this being done some decades ago, but I thought it sounded too silly to remember the details.  Actually, it was I who was silly, thinking FPGA vendors would see the wisdom of opening up their configuration formats.

Glossary:

LUT = Look-Up Table.  Most FPGAs implement logic functions with small RAMs, each of which implements an n-input arbitrary logic function using brute-force table lookup, where n is 3 to 6 depending on the FPGA.

I think we are perhaps confusing our aims a little here.

To learn basic digital logic there is nothing to beat gettting going with a breadboard and  a handful of 74 or 4000 series chips. You can see all the nodes with a cheap scope and you don't need any other tools except a pencil and paper. If you have the determination you can make some interesting stuff.

I'm not at all happy with this "teaching" talk re the RPi - I thought it was meant to be about Discovery, Invention and Improvisation such as we saw in the early days of micros and cheap home computers like the Spectrum. So I was assuming that if someone adds an FPGA to their RPi thay want to able do something exciting with it  - we can't all play with Ferraris but we can all be let  loose with a decent modern FPGA !

With regard to open source tools - as far as I can tell there aren't any worth using and the tools from the FPGA vendors need big computers to run, Linux is no problem but you need lots of RAM and lots of hard disk. No one in their right mind would want to run a  VHDL simulator doing anything much on tiny computer like the RPi (just too slow). So we may as well accept the world as it is, and right now that means FPGA simulation and compilation on a PC or MAC.

Michael Kellett

The question is: Should VHDL simulators run so slowly as they do? I think not.

SHOULD a VHDL compiler require a big computer? I think not.

If say I want to calculate pi to 1 billion decimal places I inherently need around 1Gb of memory. Or 512Mb if I go BCD. But as FPGA configurations fit in a few megabytes even for quite large ones, there is no inherent reason to that an FPGA compile needs to use large amounts of memory.

The vendor's FPGA tools have become big clunky pieces of software because they were incrementally developed by lots of different programmers.

A good Open source redesign would yield a much sleeker program.

@Roger,

As you protest that an open source FPGA design toolset would be so much better than the efforts made by several different teams of pretty good people in the FPGA industry I'm reminded of  a passage from Jane Austen's Pride and Prejudice:

During a discussion about playing the piano, Lady Catherine remarks, “If I had ever learnt, I should have been a great proficient.”

Michael Kellett

@Roger,

As you protest that an open source FPGA design toolset would be so much better than the efforts made by several different teams of pretty good people in the FPGA industry I'm reminded of  a passage from Jane Austen's Pride and Prejudice:

During a discussion about playing the piano, Lady Catherine remarks, “If I had ever learnt, I should have been a great proficient.”

Michael Kellett

Yeah, in Dutch we have the saying "De beste stuurlui staan aan wal". Litterally the best shippers are on the shore, meaning it is easy to critisize those who actually have to DO it.

And I'm sure there would be a few "snags" to work out when you'd do things again. Some of which would require more memory than I'd guess now. But having seen Quartus start up, you know immediately that there is too much bloat, as just the gui alone already takes a gigabyte of memory.

A design program like eagle has a commandline. Most don't use that. But it makes sense for design programs like eagle, mentor chip design and quartus. That means that your gui can remain quite lightweight. In eagle for instance, the gui need only startup a "show the current schematic" subprogram if the "schematic" window is open.

Michael Kellett wrote:

 

@Roger,

 

As you protest that an open source FPGA design toolset would be so much better than the efforts made by several different teams of pretty good people in the FPGA industry I'm reminded of  a passage from Jane Austen's Pride and Prejudice:

 

During a discussion about playing the piano, Lady Catherine remarks, “If I had ever learnt, I should have been a great proficient.”

Nice quote!  But the FPGA lockout reminds me of two lines from Tom Lehrer's "Whatever Became of Hubert":

Tom Lehrer sang:

 

Second fiddle's a hard part, I know,

When they don't even give you a bow.

For the record, I'm not saying open source tools would have better quality than vendors' tools.  I'm saying opening the programming bit streams would open up new applications (such as seriously-reconfigurable computing) and allow far more people to learn about FPGAs and become proficient in using them, resulting in far more FPGA chips being sold.

In any event, my question was prompted by a much less ambitious goal, a desire to have (and to help in developing) an open source EDA tool that is able to read, design for, and program some elementary programmable logic device, no matter how old and basic, as log as it's still being manufactured and sold.  That's a far cry from other worthy goals like better quality than vendors' proprietary software or less bloaty or more efficient.

Nevertheless, it would be a start, and at least for some small projects and for some types of education, I'm sure that such open tools would be perfectly adequate, no matter how unimpressive the target device.  And from small seeds can grow impressive trees.

But to do that, one first has to identify some openly documented target device, and it seems that our list of possible candidates is empty at this point.

read: http://lekernel.net/fpga_toolchain_talk.pdf

Some attempts have been made. I found several links to ulogic.com which was said to have reverse engineered a xilinx bitstream. Site has vanished.

I doubt that there is any future in an approach that relies on reverse-engineering a bitstream format.  All it would take is a small change in the format for the company's next device and you're back to square one.  While in principle your tool would still work for the old device as long as it remains in production, it's quite a bleak prospect, with no future path.

Maybe the idea is doomed until semiconductor fabrication can be done by enthusiasts / open community.

Morgaine Dinova wrote:

 

But to do that, one first has to identify some openly documented target device, and it seems that our list of possible candidates is empty at this point.

I've spent way too much time thinking about this over the last few days, and here are the best ideas I have so far:

1.  The last time I looked, it was pretty simple to find the registers that program the "12C4" PLDs in a Cypress PSoC5, which is an ARM Cortex-M3 with an attached array of digital and analogue goodness.  (There's also an 8051-based PSoC3.)  So even if you can't figure out a way to re-program the digital interconnect, you could have a fixed routing of one or more "12C4" PLDs to the I/O pins and use the ARM to talk to a RasPi for reconfiguration and internal signal probing.  This gives you one or more PLDs, with the programmer is on the same chip.

2.  As I suggested before, you could take a medium size FPGA, say a Xilinx XC3S200A, and use its LUTs as ROMs for storing logic functions and routing.  Xilinx documents how to update the contents of ROMs and registers (but not the routing).  Without a lot of effort, I think it's possible to fit in a 30-cell PLD with a simple, brute-force architecture that would permit simple tools.  Yes, you're only using a couple percent of the 200A's logic resources, but that's the nature of general-purpose computing: you spend a lot of energy getting data to the compute engines and very little doing actual computations.

The idea here is that students could get started with the PLD-within-an-FPGA with simple, clean tools that don't get in the way of learning about logic.  The students who blast through this and want to make something incredible can use the same FPGA development board and Xilinx tools to do big things, but you don't have to try to teach Verilog/VHDL and the Xilinx tool chain to everybody (including the instructors).  The US$55 XC3S200A-based XuLA-200 board form XESS  looks like a promising platform.  One thing very nice about this board is that the PIC that interfaces between USB and JTAG has GPL free-as-in-liberty software, so you can talk to it from any USB host, including RasPi, instead of being digitally handcuffed to an x86 host.  And if you want to add features like probing internal registers using JTAG you can update the PIC software with new features.

So there's a couple of ways to do this, and others may appear.  This means it's worth while to finish putting together that simple, clean CAD system I keep talking about.  We'll see what other platforms are ready when I have something working.

Morgaine Dinova wrote:

 

I doubt that there is any future in an approach that relies on reverse-engineering a bitstream format.  All it would take is a small change in the format for the company's next device and you're back to square one.  While in principle your tool would still work for the old device as long as it remains in production, it's quite a bleak prospect, with no future path.

 

Maybe the idea is doomed until semiconductor fabrication can be done by enthusiasts / open community.

The basic problem is that the vendors see no advantage in opening up their formats to the world, and a number of disadvantages.  They like to tell prospects that their format is double-secret-has-never-been-hacked, or else prospects fear that their designs will be stolen.  However, I've heard over the decades that the bit format is not that hard to reverse-engineer.  The problem is that if you publish the results you could be sued.

Now that the principal Xilinx and Altera patents have expired, maybe an Asian semiconductor manufacturer will create a line of cheap FPGAs with an open bitstream so they don't have to write tools.  The problem is that nobody will buy the parts until there are tools, and nobody will create the tools until there are parts (or at least an architecture).  If it were as cheap to make ICs as PCBs or 3-D printed thingummies, the open community could do this themselves.  Actually, it is cheap to make ICs -- just use an FPGA and the vendor's tools, so there's not really an incentive to do this.

So here's my plan: make that simple, clean CAD system and target whatever I can, be it Cypress PSoC5 or PLD-within-an-FPGA.  This at least gets the tool ball rolling, and I'll have the fun of helping kids get into logic.  "Logic!  Why don't they teach Logic in these schools?" asks the Old Professor in The Lion, the Witch, and the Wardrobe.

And who knows?  Maybe reverse-engineering for the purpose of using a manufacturer's product for the purpose intended by the manufacturer will become legal -- at least in some country -- and the bitstream formats will become legally hackable.  Or one minor vendor facing bankrupcy will open their format as a "Hail Mary" pass, and the others will fearfully follow.  After all, who expected Broadcom to open-source their OpenGL "driver"? 

Roger Wolff wrote:

 

read: http://lekernel.net/fpga_toolchain_talk.pdf

Some attempts have been made. I found several links to ulogic.com which was said to have reverse engineered a xilinx bitstream. Site has vanished.

I believe the ulogic.com site had an implementation of the work described in this paper: From the bitstream to the netlist.  Here's the key quote:

It is widely believed that the analysis of bitstream formats is a daunting task.  In fact, it is surprisingly easy.  This paper presents a methodological approach to bitstream reversing illustrated with a case study on the Virtex FPGA lines from Xilinx.

John Beetem wrote:

 

I believe the ulogic.com site had an implementation of the work described in this paper: From the bitstream to the netlist.  Here's the key quote:

It is widely believed that the analysis of bitstream formats is a daunting task.  In fact, it is surprisingly easy.  This paper presents a methodological approach to bitstream reversing illustrated with a case study on the Virtex FPGA lines from Xilinx.

Unfortunately it's a bit of a foregone conclusion that if a useful tool were ever produced after reverse-engineering the format and it gains popularity, Xilinx would respond by making their next bitstream encrypted.  And while the hardcore hackers may see that as a fun challenge, for those interested in open source engineering rather than chasing tail lights, it's a poor road to take.

John Beetem wrote:

 

1.  The last time I looked, it was pretty simple to find the registers that program the "12C4" PLDs in a Cypress PSoC5, which is an ARM Cortex-M3 with an attached array of digital and analogue goodness.  (There's also an 8051-based PSoC3.)  So even if you can't figure out a way to re-program the digital interconnect, you could have a fixed routing of one or more "12C4" PLDs to the I/O pins and use the ARM to talk to a RasPi for reconfiguration and internal signal probing.  This gives you one or more PLDs, with the programmer is on the same chip.

There could be quite a lot of milage in that approach, particularly in the light of recent developments.  I read on this page on Dangerous Prototypes' site --- freesoc-psoc-dev-board/ --- that very recently a successful Kickstarter project is aiming to produce a couple of cheap open hardware boards for PSoC5 --- http://www.kickstarter.com/projects/18182218/freesoc-and-freesoc-mini