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Raspberry Pi
Raspberry Pi Forum Help. Very confused about RP2040 PIO.
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  • raspberry_pi
  • rp2040
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Help. Very confused about RP2040 PIO.

uncountable
uncountable over 3 years ago

Hi All,

I have a very simple protocol I am trying to implement in the RP2040 PIO module. But I can't make heads or tails of the documentation from the datasheet. There is also not a single helpful example anywhere that I can find. If there is an expert on this board who could give me a couple hints of how I can do the following, I would be very appreciative.

I have a very simple protocol. I have a 6 bit bus. I need to run that bus at half the system clock (66.5 MHz). I have another pin that is the clock, which needs to toggle at system speed. (133 MHz) So an incredibly straightforward and simple, 6 bit, parallel bus streaming continuously at 66.5 MHz.  Now, I have a big block of RAM with data that I need to send out over this bus.  All I am trying to do is understand how to get these FIFO's and shift registers to do what they need to do. Unfortunately, every PIO example seems to assume that your data width is a divisor of 32.  But I don't have that.  Consider, during the first 5 clocks, I will clock out 30 bits. Now I have 2 bits left in my shift register. 

I need to understand how I can transfer, say 16 bits, from the FIFO into my shift register, so that it refills to 18 bits. I can't simply throw away those extra bits I haven't used yet. There is not a single example that I can find in any of the documents that even discusses this issue. I thought maybe I could use 3 state machines each doing 2 bits, but that doesn't work either because I can't get 3 state machines to pull from the same shift register. Maybe there is some complicated way I can tie 3 scripts together at the boundary and keep them perfectly synchronized, but then I need to be very careful to make sure DMA loads the right 32 bit word into the right FIFO at the right time, especially at startup.

What looked like a very simple and elegant solution to my problem now appears to be completely impossible due to the severe limitations of the PIO. Am I missing something about how this works? I am really surprised that the documentation around this peripheral is so dreadful, because the rest of the datasheet and SDK is actually quite good.

I would love to hear any advice or possible solutions from somebody with experience in this area. I can't change the data ordering in RAM. I can barely keep the pipeline full as it is using both cores at 90%. I really hate to abandon the part, because at the price point nothing else can touch it.

Thanks in advance.

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  • scottiebabe
    0 scottiebabe over 3 years ago

    Of course its possible to clock out 6bits at time taking in 32-bit fifo data. But that requires using some of the PIO instructions, which would limit your throughput.

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  • phoenixcomm
    0 phoenixcomm over 3 years ago in reply to scottiebabe

    I just looked at the "manual" you can use 6 gio pins for the data how do figure that I will limit the throughput when there is no data (that I found) to support this? 

    BTW its a cool part but all they do is talk about clock cycles. there are no detaT specs anywhere. and if you are using a 32 bit serial output that means you have to SHIFT each bit 32 times. fun So in my way of thinking (which could be wrong) parallel output should be faster., and would do the job. 

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  • phoenixcomm
    0 phoenixcomm over 3 years ago in reply to scottiebabe

    I just looked at the "manual" you can use 6 gio pins for the data how do figure that I will limit the throughput when there is no data (that I found) to support this? 

    BTW its a cool part but all they do is talk about clock cycles. there are no detaT specs anywhere. and if you are using a 32 bit serial output that means you have to SHIFT each bit 32 times. fun So in my way of thinking (which could be wrong) parallel output should be faster., and would do the job. 

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  • scottiebabe
    0 scottiebabe over 3 years ago in reply to phoenixcomm

    LOL you are quite right, the datasheet has no timing specs... 

    If the OP only placed 5, 6-bit fields into a 32-bit word, ( a 32/30 increase in ram usage), the PIO routine would be a mere 2 instruction PIO routine.  

    It is the bit twiddling to stich together the bit field that straddles 2 32-bit words that would take a couple of PIO instructions.

    The OP could try to pipeline the operation by having one PIO state machine dma piped to the next. The first state machine unpacks the 32-bit data stream into a 30-bit wide data stream so the second PIO is easy-peasy. 

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  • phoenixcomm
    0 phoenixcomm over 3 years ago in reply to scottiebabe

    Ok, cool piece of junk. just not the right thing for the job. maybe he should look at  this is more likely a better way to go 

    EK-TM4C123GXL TivaTm C Series TM4C123G LaunchPad and its less than $20.00

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  • cstanton
    0 cstanton over 3 years ago in reply to scottiebabe
    scottiebabe said:
    the datasheet has no timing specs

    This would be a good question for the RP2040 software developer that will be doing a webinar on the Community on , I think, the 29th of september.

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  • scottiebabe
    0 scottiebabe over 3 years ago in reply to cstanton

    lol I wouldn't want to throw the presenter under the bus (today's presenter's words). Perhaps collecting the questions in advance using the new voting tool could be helpful, /challenges-projects/project14/i/themesuggestions 

    I would like to know why the sleep current with all clocks disabled is almost 1 mA... That's a lot for a battery powered device when sleeping/idling.

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  • cstanton
    0 cstanton over 3 years ago in reply to scottiebabe
    scottiebabe said:
    to throw the presenter under the bus

    Phil was being a bit hyperbole when he said that. 

    The webinars are entirely purposeful for being there to ask these sorts of questions. The presenter today was more about the general applications rather than the specific implementations.

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  • scottiebabe
    0 scottiebabe over 3 years ago in reply to cstanton

    I think it was the RPI presenter who said it, but it clearly was said with no ill intentions :) I enjoyed the webinar, I thought it was well done!

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