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Help. Very confused about RP2040 PIO.

uncountable

Hi All,

I have a very simple protocol I am trying to implement in the RP2040 PIO module. But I can't make heads or tails of the documentation from the datasheet. There is also not a single helpful example anywhere that I can find. If there is an expert on this board who could give me a couple hints of how I can do the following, I would be very appreciative.

I have a very simple protocol. I have a 6 bit bus. I need to run that bus at half the system clock (66.5 MHz). I have another pin that is the clock, which needs to toggle at system speed. (133 MHz) So an incredibly straightforward and simple, 6 bit, parallel bus streaming continuously at 66.5 MHz.  Now, I have a big block of RAM with data that I need to send out over this bus.  All I am trying to do is understand how to get these FIFO's and shift registers to do what they need to do. Unfortunately, every PIO example seems to assume that your data width is a divisor of 32.  But I don't have that.  Consider, during the first 5 clocks, I will clock out 30 bits. Now I have 2 bits left in my shift register. 

I need to understand how I can transfer, say 16 bits, from the FIFO into my shift register, so that it refills to 18 bits. I can't simply throw away those extra bits I haven't used yet. There is not a single example that I can find in any of the documents that even discusses this issue. I thought maybe I could use 3 state machines each doing 2 bits, but that doesn't work either because I can't get 3 state machines to pull from the same shift register. Maybe there is some complicated way I can tie 3 scripts together at the boundary and keep them perfectly synchronized, but then I need to be very careful to make sure DMA loads the right 32 bit word into the right FIFO at the right time, especially at startup.

What looked like a very simple and elegant solution to my problem now appears to be completely impossible due to the severe limitations of the PIO. Am I missing something about how this works? I am really surprised that the documentation around this peripheral is so dreadful, because the rest of the datasheet and SDK is actually quite good.

I would love to hear any advice or possible solutions from somebody with experience in this area. I can't change the data ordering in RAM. I can barely keep the pipeline full as it is using both cores at 90%. I really hate to abandon the part, because at the price point nothing else can touch it.

Thanks in advance.

  • 0

    It looks like my graphic did not get added, and I can't figure out how to edit the post to add it. Let me try it here instead. This is the part of the datasheet I find confusing. If someone can shed light on the details of how this mux and shifter actually work, I would be grateful.

    image

  • 0

    Hi,

    I know very little (~0) about the PIO, so I may be talking complete nonsense. As I understand, the FIFOs' are 32-bit wide, and are only ever transferred in 32 bits at a time, i.e. it's impossible to pass in just 16 bits into the shift register. I think you're right, either some scheme to use multiple state machines would be needed, which I can't think of but could be possible, or alternatively you may need to consider a solution where the data ordering in RAM can be changed (I know you stated you cannot, but perhaps it's ok to ignore some parts of the RAM content, so that you're not reordering as such, but loading in data while throwing away some bits: for instance, would it be possible to just use 8 outputs instead, and ignore two of them. In other words, two bits, or 25% of throughput would be effectively wasted, but I guess that may not matter, since all you're concerned about is the 6 bits. But it would require losing two bits of RAM per byte.

  • 0

    You can't get there from here. 

    You could just some of the PIOs and get it over with it. KISS!!! wins again. 

  • 0 in reply to uncountable

    Its is quite possible the "Output Shift Register" is just the register of the OSR. But the documentation could be clearer. All 3 blocks together form the OSR.

  • 0

    Of course its possible to clock out 6bits at time taking in 32-bit fifo data. But that requires using some of the PIO instructions, which would limit your throughput.

  • 0 in reply to uncountable

    The Raspberry Pi Pico C/C++ SDK document should provide the answers. Suggest looking at the OUT instruction... SDK document notes:

    "Shift Bit count bits out of the Output Shift Register (OSR), and write those bits to Destination . Additionally, increase the output shift count by Bit count, saturating at 32."

    "If automatic pull is enabled, the OSR is automatically refilled from the TX FIFO if the pull threshold, SHIFTCTRL_PULL_THRESH, is reached. The output shift count is simultaneously cleared to 0. In this case, the OUT will stall if the TX FIFO is empty, but otherwise still executes in one cycle."

  • 0 in reply to scottiebabe

    I just looked at the "manual" you can use 6 gio pins for the data how do figure that I will limit the throughput when there is no data (that I found) to support this? 

    BTW its a cool part but all they do is talk about clock cycles. there are no detaT specs anywhere. and if you are using a 32 bit serial output that means you have to SHIFT each bit 32 times. fun So in my way of thinking (which could be wrong) parallel output should be faster., and would do the job. 

  • 0 in reply to phoenixcomm

    LOL you are quite right, the datasheet has no timing specs... 

    If the OP only placed 5, 6-bit fields into a 32-bit word, ( a 32/30 increase in ram usage), the PIO routine would be a mere 2 instruction PIO routine.  

    It is the bit twiddling to stich together the bit field that straddles 2 32-bit words that would take a couple of PIO instructions.

    The OP could try to pipeline the operation by having one PIO state machine dma piped to the next. The first state machine unpacks the 32-bit data stream into a 30-bit wide data stream so the second PIO is easy-peasy. 

  • 0 in reply to scottiebabe

    Ok, cool piece of junk. just not the right thing for the job. maybe he should look at  this is more likely a better way to go 

    EK-TM4C123GXL TivaTm C Series TM4C123G LaunchPad and its less than $20.00

  • 0 in reply to BigG

    You should take a look at the official PIO examples available on GitHub. The two examples, which may be of help are clocked_input, i2c and manchester_encoding. If you look at the initialisation routine in the PIO files you will notice a couple of FIFO related define functions which may help you.

    static void sm_config_set_in_shift (pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold)

    static void sm_config_set_out_shift (pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold)

    static void sm_config_set_fifo_join (pio_sm_config *c, enum pio_fifo_join join)

    These allow to to define your thresholds for your fifo and they allow you to set autopush for the fifo.

    The fifo_join function also allows for more clever stuff (it's used int he manchester_encoding example).

    Happy coding.