Hi All,
I have a very simple protocol I am trying to implement in the RP2040 PIO module. But I can't make heads or tails of the documentation from the datasheet. There is also not a single helpful example anywhere that I can find. If there is an expert on this board who could give me a couple hints of how I can do the following, I would be very appreciative.
I have a very simple protocol. I have a 6 bit bus. I need to run that bus at half the system clock (66.5 MHz). I have another pin that is the clock, which needs to toggle at system speed. (133 MHz) So an incredibly straightforward and simple, 6 bit, parallel bus streaming continuously at 66.5 MHz. Now, I have a big block of RAM with data that I need to send out over this bus. All I am trying to do is understand how to get these FIFO's and shift registers to do what they need to do. Unfortunately, every PIO example seems to assume that your data width is a divisor of 32. But I don't have that. Consider, during the first 5 clocks, I will clock out 30 bits. Now I have 2 bits left in my shift register.
I need to understand how I can transfer, say 16 bits, from the FIFO into my shift register, so that it refills to 18 bits. I can't simply throw away those extra bits I haven't used yet. There is not a single example that I can find in any of the documents that even discusses this issue. I thought maybe I could use 3 state machines each doing 2 bits, but that doesn't work either because I can't get 3 state machines to pull from the same shift register. Maybe there is some complicated way I can tie 3 scripts together at the boundary and keep them perfectly synchronized, but then I need to be very careful to make sure DMA loads the right 32 bit word into the right FIFO at the right time, especially at startup.
What looked like a very simple and elegant solution to my problem now appears to be completely impossible due to the severe limitations of the PIO. Am I missing something about how this works? I am really surprised that the documentation around this peripheral is so dreadful, because the rest of the datasheet and SDK is actually quite good.
I would love to hear any advice or possible solutions from somebody with experience in this area. I can't change the data ordering in RAM. I can barely keep the pipeline full as it is using both cores at 90%. I really hate to abandon the part, because at the price point nothing else can touch it.
Thanks in advance.
