Those of you who are familiar with desktop or laptop computers will already be familiar with "northbridge" and "southbridge" types of chips. These are common on motherboards these days and compliment the central processing unit and graphics processing unit in your computer.
Usually, a northbridge chipset handles integration between CPU, PCI-E and RAM devices, where as the southbridge communicates with the northbridge and any further, external or legacy or basic components. Such as USB, ISA, BIOS, PCI, IDE, etc.
The Raspberry Pi 5 integrates a southbridge chip, the RP1.
Not a great deal is known about this chip yet, the datasheets haven't been fully revealed or distributed, however there have been some discussions about it in various places by the engineers from Raspberry Pi, and Luke Wren has something to say about its capabilities:
If you're unable to read the image it says:
"There is one PIO instance (4 state machines). It's identical to the PIO blocks on RP2040, except the FIFO depth is doubled. It has single-cycle bus access from the dual Cortex-M3 management processors on RP1, and the PIO FIFOs can also be accessed from the host processor (2712) over PCIe, but the PIO configuration registers are only accessible to the RP1 processors.
One of RP1's Cortex-M3s is currently going spare, so it should be possible to write your own Cortex-M firmware and load it into the 16 kB per-Cortex-M3 private SRAM. There won't be any software support for this at launch though."
Luke further elaborates on this on X / Twitter:
I want to walk back that point about PCIe access to FIFOs. The PIO block's AHB port is connected to RP1's processor fabric, and we added a second bus interface which exposes (just) the FIFOs to RP1's system bus fabric, so that RP1's internal DMA can access the FIFOs. This ...
... does also expose them over PCIe, since there is a route from 2712's PCIe windows through to the top of RP1's system fabric, but this is not actually usable for host transfers since you can't access the status registers.
Using RP1's PIO requires firmware running on RP1.
But yeah, there's a PIO block in there, we're putting that bad boy in everything from now on
It would appear that we have another microprocessor to play with! Though for most it will not be a trivial component to handle, and there's no software support for it (just yet). Perhaps those of you that were hoping for an embedded RP2040 can play with this instead?
